On applying the set covering model to reseeding

The Functional BIST approach is a rather new BIST technique based on exploiting embedded system functionality to generate deterministic test patterns during BIST. The approach takes advantages of two well-known testing techniques, the arithmetic BIST approach and the reseeding method. The main contribution of the present paper consists in formulating the problem of an optimal reseeding computation as an instance of the set covering problem. The proposed approach guarantees high flexibility, is applicable to different functional modules, and, in general, provides a more efficient test set encoding then previous techniques. In addition, the approach shorts the computation time and allows to better exploiting the tradeoff between area overhead and global test length as well as to deal with larger circuits

AFSM-based deterministic hardware TPG

This paper proposes a new approach for designing a cost-effective, on-chip, hardware pattern generator of deterministic test sequences. Given a pre-computed test pattern (obtained by an ATPG tool) with predetermined fault coverage, a hardware Test Pattern Generator (TPG) based on Autonomous Finite State Machines (AFSM) structure is synthesized to generate it. This new approach exploits "don't care" bits of the deterministic test patterns to lower area overhead of the TPG. Simulations using benchmark circuits show that the hardware components cost is considerably less when compared with alternative solution

Acceleration of Seed Ordering and Selection for High Quality Delay Test

Seed ordering and selection is a key technique to provide high-test quality with limited resources in Built-In Self Test (BIST) environment. We present a hard-to-detect delay fault selection method to accelerate the computation time in seed ordering and selection processes. This selection method can be used to restrict faults for test generation executed in an early stage in seed ordering and selection processes, and reduce a test pattern count and therefore a computation time. We evaluate the impact of the selection method both in deterministic BIST, where one test pattern is decoded from one seed, and mixed-mode BIST, where one seed is expanded to two or more patterns. The statistical delay quality level (SDQL) is adopted as test quality measure, to represent ability to detect small delay defects (SDDs). Experimental results show that our proposed method can significantly reduce computation time from 28% to 63% and base set seed counts from 21% to 67% while slightly sacrificing test quality

Acceleration of Seed Ordering and Selection For High Quality VLSI Delay Test

Seed ordering and selection is a key technique to provide high-test quality with limited resources in Built-In Self Test (BIST) environment. We present a hard-to-detect delay fault selection method to optimize the computation time in seed ordering and selection processes. This selection method can be used to select faults for test generation when it is impractical to target all delay faults resulting large test pattern count and long Computation time. Three types of selection categories are considered, ranged in the number of seeds it produced, which is useful when we consider computing resources, such as memory and storage. We also evaluate the impact of the selection method in mixed-mode BIST when seed are expanded to more patterns, and evaluate the statistical delay quality level (SDQL) with the original work. Experimental results show that our proposed method can significantly reduce computation time while slightly sacrificing test quality

BIST : respuesta a los nuevos desafíos para el test de sistemas en chip (I)

Las técnicas DIST posibilitan que un circuito integrado realice su propio test por sí mismo. BIST reduce los costes de test y mantenimiento para sistemas en chip gracias a la eliminación de costosos equipos externos de test y permitiendo la localización de circuitos defectuosos dentro de sistemas. DIST puede llevar a cabo el test a la frecuencia normal de funcionamiento del diseño, lo que es fundamental a la hora de detección de fallos relativos a la temporización. A pesar de estas ventajas, BIST ha tenido y tiene un uso muy limitado en la industria porque añade más área al circuito e incrementa el tiempo de diseño.Peer Reviewe

Improving timing verification and delay testing methodologies for IC designs

textThe task of ensuring the correct temporal behavior of IC designs, both before and after fabrication, is extremely important. It is becoming even more imperative as the demand for performance increases and process technology advances into the deep sub-micron region. This dissertation tackles the key issues in the timing verification and delay testing methodologies. An efficient methodology is presented to identify false timing paths in the timing verification methodology which utilizes ATPG technique and timing information from an ordered list of timing paths according to the delay information. This dissertation also presents a speed binning methodology which utilizes structural delay tests successfully instead of functional tests. In addition, it establishes a methodology which quantifies the correlation between the timing verification prediction and actual silicon measurement of timing paths. This quantification methodology lays the foundation for further research to study the impact of deep submicron effects on design performanceElectrical and Computer Engineerin

A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits

[[abstract]]During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns can't detect fault (called useless patterns). In order to reduce the test time, we can remove useless patterns or change them to useful patterns (fault dropping). In fact, a random test set includes many useless patterns. Therefore we present a technology, including both reseeding and bit modifying (a.k.a. pattern mapping) to remove useless patterns or change them to useful patterns. When patterns changed, we pick out number of different fewer bits, leading to very short test length. Then we use an additional bit counter to improve test length and achieve high fault coverage. The technique we present is applicable for single-stuck-at faults. Experimental results indicate that complete fault coverage-100% can be obtained with less test time.[[notice]]補正完畢[[journaltype]]國際[[incitationindex]]EI[[ispeerreviewed]]Y[[booktype]]紙本[[countrycodes]]TW