Synthesis Optimization on Galois-Field Based Arithmetic Operators for Rijndael Cipher

A  series  of  experiments  has  been  conducted  to  show  that  FPGA synthesis  of  Galois-Field  (GF)  based  arithmetic  operators  can  be  optimized automatically  to  improve  Rijndael  Cipher  throughput.  Moreover,  it  has  been demonstrated  that  efficiency  improvement  in  GF  operators  does  not  directly correspond to the system performance at application level. The experiments were motivated by so many research works that focused on improving performance of GF  operators.  Each  of  the  variants  has  the  most  efficient  form  in  either  time (fastest) or space  (smallest occupied area) when implemented in FPGA chips. In fact,  GF  operators are not utilized  individually, but  rather integrated one to the others to  implement algorithms.  Contribution  of  this  paper  is  to  raise  issue  on GF-based  application  performance  and  suggest  alternative  aspects  that potentially  affect  it.  Instead  of  focusing  on  GF  operator  efficiency,  system characteristics are worth considered in optimizing application performance

Towards a triple mode common operator FFT for Software Radio systems

International audienceA scenario to design a Triple Mode FFT is addressed. Based on a Dual Mode FFT structure, we present a methodology to reach a triple mode FFT operator (TMFFT) able to operate over three different fields: complex number domain C, Galois Fields GF(Ft) and GF(2m). We propose a reconfigurable Triple mode Multiplier that constitutes the core of the Butterflybased FFT. A scalable and flexible unit for the polynomial reduction needed in the GF(2m) multiplication is also proposed. An FPGA implementation of the proposed multiplier is given and the measures show a gain of 18%in terms of performance-to-cost ratio compared to a "Velcro" approach where two self-contained operators are implemented separately

Generalized polyphase representation and application to coding gain enhancement

Generalized polyphase representations (GPP) have been mentioned in literature in the context of several applications. In this paper, we provide a characterization for what constitutes a valid GPP. Then, we study an application of GPP, namely in improving the coding gains of transform coding systems. We also prove several properties of the GPP

VLSI Implementation of Block Error Correction Coding Techniques

Communication Engineering has become the most vital field of Engineering in today’s life. The world is dreaded to think beyond any communication gadgets. Data communication basically involves transfers of data from one place to another or from one point of time to another. Error may be introduced by the channel which makes data unreliable for user. Hence we need different error detection and error correction schemes. In the present work, we perform the comparative study between different FECs like Turbo codes, Reed-Solomon codes and LPDC codes. But among all these we find Reed Solomon to be most efficient for data communication because of low coding complexity and high coding rate. The RS codes are non-binary, linear and cyclic codes used for burst error correction. They are used in numerous applications like CDs, DVDs and deep space communication. We simulate RS Encoder and RS Decoder for double error correcting RS (7, 3) code. Then we implement RS (255,239) code in VHDL. In RS (255,239) code, each data symbol consists of 8 bits which is quite practical as most of the data transfer is done in terms of bytes. The implementation has been done in the most efficient algorithms to optimize the design in terms of space utilization and latency of the code. The behavioral simulation has been carried out for each block and for the whole design also. Finally, the FPGA utilization and clock cycles needed are analyzed and compared with the already developed designs

High-Speed Area-Efficient Hardware Architecture for the Efficient Detection of Faults in a Bit-Parallel Multiplier Utilizing the Polynomial Basis of GF(2m)

The utilization of finite field multipliers is pervasive in contemporary digital systems, with hardware implementation for bit parallel operation often necessitating millions of logic gates. However, various digital design issues, whether natural or stemming from soft errors, can result in gate malfunction, ultimately leading to erroneous multiplier outputs. Thus, to prevent susceptibility to error, it is imperative to employ an effective finite field multiplier implementation that boasts a robust fault detection capability. This study proposes a novel fault detection scheme for a recent bit-parallel polynomial basis multiplier over GF(2m), intended to achieve optimal fault detection performance for finite field multipliers while simultaneously maintaining a low-complexity implementation, a favored attribute in resource-constrained applications like smart cards. The primary concept behind the proposed approach is centered on the implementation of a BCH decoder that utilizes re-encoding technique and FIBM algorithm in its first and second sub-modules, respectively. This approach serves to address hardware complexity concerns while also making use of Berlekamp-Rumsey-Solomon (BRS) algorithm and Chien search method in the third sub-module of the decoder to effectively locate errors with minimal delay. The results of our synthesis indicate that our proposed error detection and correction architecture for a 45-bit multiplier with 5-bit errors achieves a 37% and 49% reduction in critical path delay compared to existing designs. Furthermore, the hardware complexity associated with a 45-bit multiplicand that contains 5 errors is confined to a mere 80%, which is significantly lower than the most exceptional BCH-based fault recognition methodologies, including TMR, Hamming's single error correction, and LDPC-based procedures within the realm of finite field multiplication.Comment: 9 pages, 4 figures. arXiv admin note: substantial text overlap with arXiv:2209.1338