High Speed Low Area DA Based FIR Filter Using EGDI Adder

In this paper, we proposed a novel enhanced gate diffusion (EGDI) adder is designed and is implemented in Distributed Arithmetic (DA) based Finite Impulse Response (FIR) filter.  Generally, multipliers, adders, and shift accumulators are the basic blocks present in the FIR filters. The hardware architecture of multipliers is very high. To get rid of this multiplier less architecture is needed in the FIR filter. So Distributed Arithmetic architecture plays a key role in FIR filters which will occupy less area and increase the speed. To reduce the area further the adders in DA are designed using enhanced gate diffusion (EGDI) which increases the operation speed of the FIR filter and at the same time, the area will be decreased. The proposed design is synthesized and implemented in the Synapsis design compiler tool. The area, power delay product, frequency, area delay product, and power of the proposed design are calculated.  When we observe the proposed design has a 15% high-frequency rate when compared with the existing design. Also, the proposed design is more useful in signal, processing applications

High Speed Low Area DA Based FIR Filter Using EGDI Adder

In this paper, we proposed a novel enhanced gate diffusion (EGDI) adder is designed and is implemented in Distributed Arithmetic (DA) based Finite Impulse Response (FIR) filter.  Generally, multipliers, adders, and shift accumulators are the basic blocks present in the FIR filters. The hardware architecture of multipliers is very high. To get rid of this multiplier less architecture is needed in the FIR filter. So Distributed Arithmetic architecture plays a key role in FIR filters which will occupy less area and increase the speed. To reduce the area further the adders in DA are designed using enhanced gate diffusion (EGDI) which increases the operation speed of the FIR filter and at the same time, the area will be decreased. The proposed design is synthesized and implemented in the Synapsis design compiler tool. The area, power delay product, frequency, area delay product, and power of the proposed design are calculated.  When we observe the proposed design has a 15% high-frequency rate when compared with the existing design. Also, the proposed design is more useful in signal, processing applications

Design and implementation of DA FIR filter for bio-inspired computing architecture

This paper elucidates the system construct of DA-FIR filter optimized for design of distributed arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly coupled co-processor based data processing units. With a series of look-up-table (LUT) accesses in order to emulate multiply and accumulate operations the constructed DA based FIR filter is implemented on FPGA. The very high speed integrated circuit hardware description language (VHDL) is used implement the proposed filter and the design is verified using simulation. This paper discusses two optimization algorithms and resulting optimizations are incorporated into LUT layer and architecture extractions. The proposed method offers an optimized design in the form of offers average miminimizations of the number of LUT, reduction in populated slices and gate minimization for DA-finite impulse response filter. This research paves a direction towards development of bio inspired computing architectures developed without logically intensive operations, obtaining the desired specifications with respect to performance, timing, and reliability

Using of Residual Number System as a Mathematical Basis for Software Defined Radio

Вступ. У традицiйному виглядi, програмно-визначена радiосистема (Software Defined Radio, SDR) являє собою обчислювальне ядро, обладнане приймально-передавальними блоками. З метою прискорення обчислювальних операцiй у системах SDR, пропонується у якостi математичної основи застосування системи залишкових класiв. Результати попереднiх дослiджень, що проводились рiзними групами вчених з метою пошукiв шляхiв пiдвищення продуктивностi обчислювальних засобiв, методiв органiзацiї ефективної системи виявлення та виправлення помилок, а також побудови надiйних обчислювальних комплексiв, дають можливiсть стверджувати, що в межах позицiйних систем числення не можна очiкувати принципових зрушень в даних напрямках без суттєвого збiльшення робочих частот i ускладнення апаратної частини. Перевагою пропонованого методу є те, що програмна радiосистема може складатися з декiлькох ПЛIС i обслуговувати декiлька незалежних радiоканалiв, а перепрограмування властивостей дозволяє змiнювати число i складовi процесу обробки повiдомлень в залежностi вiд поточних умов роботи. Метод дослiдження. В роздiлi проаналiзовано паралельнiсть арифметичнi операцiї у системi залишкових класiв. Цi операцiї називаються модульними, оскiльки для обробки числових значень використовують невеликi залишки дiлення на певний набiр модулiв, а для додавання i множення потрiбно лише один тактовий цикл роботи обчислювальної системи. Для перетворення чисел iз двiйкової системи у RNS використовується алгоритм, заснований на застосуваннi китайської теореми про залишки. Проте такi операцiї, як подiл, порiвняння двох чисел i виявлення знака, є складними i ресурсо-затратними в RNS. Для цих проблемних операцiй було запропоновано кiлька рiшень. Вони полягають у вiдсутностi процесу перетвореннi залишку в бiнарну систему (зворотне перетворення) шляхом застосування цифро-аналогових перетворювачiв у RNS. З iншого боку, вибiр правильного набору модулiв є ще одним важливим питанням для побудови ефективного RNS з достатнiм динамiчним дiапазоном. Результати та аналiз. Пiдводячи пiдсумки деяких результатiв, можна зазначити, що система класiв залишкiв дозволяє значно полiпшити параметри обчислювача у SDR, а особливо у функцiональному блоковi Direct Digital Synthesizers (DDS) у порiвняннi з обчислювачем, побудованим на тiй же фiзичнiй i технологiчнiй основi, але в позицiйнiй обчислювальнiй системi, а також отримання нових бiльш прогресивних конструктивних i структурних рiшень. Експериментальнi результати показують, що представленi методи дають значнi переваги для цифрових фiльтрiв у SDR, якi характеризуються високим динамiчним дiапазоном i мають велику кiлькiстю ланок, особливо коли повнi перемножувачi не доступнi у цiльовiй архiтектурi FPGA, або коли цi перемножувачi повиннi використовуватися для рiзних цiлей. Висновки. Таким чином, запропонована система вносить явнi переваги перед iснуючими системами i показує переваги продуктивностi обчислювальних операцiй i може бути використана для побудови сучасних систем зв’язку. Запропонована архiтектура зменшує розмiри конвеєру суматорiв i перемножувачiв, що є дуже важливим фактором при розробцi високошвидкiсних SDR.Introduction. In the classic view, program-defined radio system (Software Defined Radio, SDR) is a central processor, equipped with receiving and transmitting units. In order to speed up computational operations in SDR systems it is proposed to use the system of residual classes as a mathematical basis. The results of research conducted by various groups of scientists in order to find ways to improve the performance of computing tools, methods of organizing an effective system for detecting and correcting errors, as well as building reliable computer systems, make it possible to assert that, within the limits of positional number systems, no fundamental changes can be expected in these areas without a significant increase in operating frequencies and hardware complications. The advantage of this method is that a software radio system can consist of several FPGAs and serve several independent radio channels, and reprogramming the properties allows you to change the number and components of message processors depending on current operating conditions. Research method. The equations in this section show the parallel nature of the RNS, free from bit transfers. These operations are called modular, because for it takes only one clock cycle to process the numerical values. To convert numbers from the binary position number system to RNS we use an algorithm based on the application of a distributed arithmetic. However, operations such as division, comparison of two numbers, and the detection of a sign are laborious and expensive in RNS Several decisions were proposed for these problem operations. They consist in the absence of the process of converting a residue into a binary system (reverse transformation) by using digital-to-analog converters in RNS. On the other hand, choosing the right set of modules is another important issue for building an effective RNS with a sufficient dynamic range. Results and analysis. Summing up some results, it can be noted that the system of residual classes allows to significantly improve the parameters of a computer in SDR especially in functional block a Direct Digital Synthesizers (DDS) in comparison with a computer built on the same physical and technological basis, but in a positional system calculation, and also to receive new more progressive constructive and structural solutions. The experimental results shows that the presented techniques offer interesting advantages for FIR filters characterized by high dynamic range and high number of taps especially when full custom multipliers are not available in the target FPGA architecture or when they must to be used for different purposes. Conclusion. Thus, the proposed system introduces clear advantages over existing systems and shows performance advantages and can be used to build modern communication systems. The proposed architecture reduces the size of the pipeline adders and multipliers which is a very important factor in the design SDR for fast work.В статье рассмотрены принципы построения и функционирования систем, определенных программным обеспечением (Software Defned Radio, SDR). С целью ускорения вычислительных операций в системах SDR предлагается применение системы остаточных классов в качестве математической основы построения систем. Преимуществом приведенного метода является то, что программная радиосистема может состоять из нескольких ПЛИС и обслуживать несколько независимых радиоканалов, а перепрограммирование свойств позволяет изменять число и составляющие процессоры сообщений в зависимости от текущих условий роботы. Приведены проблемы формирования выходного сигнала. Описаны особенности внедрения операций прямого и обратного преобразований с позиционных на непозиционые системы исчисления. Рассмотрена структурная модель SDR с прямыми цифровыми синтезаторами частоты, ЦАП, АЦП, цифровыми фильтрами в системе остаточных классов. Рассмотрены методы преобразования системы остаточных класов в аналоговый сигнал. Рассматриваются проблемы эффективного использования площади кристалла для SDR и уменьшения задержек в формировании выходного сигнала. Полученные результаты показывают широкие возможности применения программно определенной радиосистемы в системе остаточных классов

Algorithms and VLSI architectures for parametric additive synthesis

A parametric additive synthesis approach to sound synthesis is advantageous as it can model sounds in a large scale manner, unlike the classical sinusoidal additive based synthesis paradigms. It is known that a large body of naturally occurring sounds are resonant in character and thus fit the concept well. This thesis is concerned with the computational optimisation of a super class of form ant synthesis which extends the sinusoidal parameters with a spread parameter known as band width. Here a modified formant algorithm is introduced which can be traced back to work done at IRCAM, Paris. When impulse driven, a filter based approach to modelling a formant limits the computational work-load. It is assumed that the filter's coefficients are fixed at initialisation, thus avoiding interpolation which can cause the filter to become chaotic. A filter which is more complex than a second order section is required. Temporal resolution of an impulse generator is achieved by using a two stage polyphase decimator which drives many filterbanks. Each filterbank describes one formant and is composed of sub-elements which allow variation of the formant’s parameters. A resource manager is discussed to overcome the possibility of all sub- banks operating in unison. All filterbanks for one voice are connected in series to the impulse generator and their outputs are summed and scaled accordingly. An explorative study of number systems for DSP algorithms and their architectures is investigated. I invented a new theoretical mechanism for multi-level logic based DSP. Its aims are to reduce the number of transistors and to increase their functionality. A review of synthesis algorithms and VLSI architectures are discussed in a case study between a filter based bit-serial and a CORDIC based sinusoidal generator. They are both of similar size, but the latter is always guaranteed to be stable

Automatisoitu vuo suodinten laitteistokuvauksen tuottamiseen

Digitaalisia suotimia käytetään signaalien käsittelyyn monilla eri tekniikan alueilla, kuten telekommunikaatiossa, kuvankäsittelyssä ja lääketieteellisissä laitteissa. Ne ovat niin yleisiä, että insinöörit käyttävät paljon aikaa ja resursseja niiden toteuttamiseen ja verifioimiseen. Koska yleisimpien suotimien rakenne on melko yksinkertainen, niiden luominen voidaan automatisoida generaattorin avulla. Tässä diplomityössä Nokia Networksin vaatimukset kartoitetaan automatisoidun suodinten laitteistokuvauksen tuottamisvuon kehittämiseksi. Erilaisia tuottamismenetelmiä vertaillaan, mutta lopulta päädytään kehittämään oma generaattori. Se luo suotimia yhdistelemällä osia käsinkirjoitetusta RTL:stä. Lopputuloksena on automatisoitu vuo, joka tukee vakiokertoimilla varustettuja, yhden tai useamman kanavan FIR-suotimia. Käyttäjän tulee syöttää kertoimet ja haluttu datanleveys Matlab-skriptiin. Ajettaessa skripti luo suotimen ja verifioi sen. Vuo tukee sekä ASIC- että FPGA-teknologioita.Digital filters are used to process signals in many fields like telecommunications, image processing and in medical equipment. They are so omnipresent that engineers are building and verifying those all the time, using a lot of resources. As the structure of a basic filter is quite simple, savings could be made by automatizing the creation of filters. In this Thesis the requirements of Nokia Networks are analyzed to build an automatized filter generation flow. Different tools are evaluated, but finally a custom generator is built. It crafts filters from pieces of hand-written RTL. The end result is an automated flow which supports single and multichannel FIR filters with constant coefficients. The user has to input the coefficients to a Matlab script with the desired data widths. The filter is then generated and verified by running the script. The flow supports both ASIC and FPGA technologies

Application-Specific Number Representation

Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), enable application- specific number representations. Well-known number formats include fixed-point, floating- point, logarithmic number system (LNS), and residue number system (RNS). Such different number representations lead to different arithmetic designs and error behaviours, thus produc- ing implementations with different performance, accuracy, and cost. To investigate the design options in number representations, the first part of this thesis presents a platform that enables automated exploration of the number representation design space. The second part of the thesis shows case studies that optimise the designs for area, latency or throughput from the perspective of number representations. Automated design space exploration in the first part addresses the following two major issues: ² Automation requires arithmetic unit generation. This thesis provides optimised arithmetic library generators for logarithmic and residue arithmetic units, which support a wide range of bit widths and achieve significant improvement over previous designs. ² Generation of arithmetic units requires specifying the bit widths for each variable. This thesis describes an automatic bit-width optimisation tool called R-Tool, which combines dynamic and static analysis methods, and supports different number systems (fixed-point, floating-point, and LNS numbers). Putting it all together, the second part explores the effects of application-specific number representation on practical benchmarks, such as radiative Monte Carlo simulation, and seismic imaging computations. Experimental results show that customising the number representations brings benefits to hardware implementations: by selecting a more appropriate number format, we can reduce the area cost by up to 73.5% and improve the throughput by 14.2% to 34.1%; by performing the bit-width optimisation, we can further reduce the area cost by 9.7% to 17.3%. On the performance side, hardware implementations with customised number formats achieve 5 to potentially over 40 times speedup over software implementations

Acoustic Feedback Noise Cancellation in Hearing Aids Using Adaptive Filter

To enhance speech intelligibility for people with hearing loss, hearing aids will amplify speech using gains derived from evidence-based prescriptive methods, in addition to other advanced signal processing mechanisms. While the evidence supports the use of hearing aid signal processing for speech intelligibility, these signal processing adjustments can also be detrimental to hearing aid sound quality, with poor hearing aid sound quality cited as a barrier to device adoption. In general, an uncontrolled environment may contain degradation components like background noise, speech from other speakers etc. along with required speech components. In this paper, we implement adaptive filtering design for acoustic feedback noise cancellation in hearing aids. The adaptive filter architecture has been designed using normalized least mean square algorithm. By using adaptive filters both filter input coefficients are changeable during run-time and reduce noise in hearing aids. The proposed design is implemented in matlab and the simulations shows that the proposed architecture produces good quality of speech, accuracy, maintain stable steady state. The proposed design is validated with parameters like Noise Distortion, Perceptual Evaluation of Speech Quality, Signal to Noise Ratio, and Speech Distortion. The feedback canceller is implemented in MATLAB 9.4 simulink version release name of R2018a is used for validation with Echo Return Loss Enhancement (ERLE). The ERLE of the NMLS is reduced when the filter order is increases. Around 10% of the power spectrum density (PSD) is less when compared with existing designs

Automatisoitu vuo suodinten laitteistokuvauksen tuottamiseen

Digitaalisia suotimia käytetään signaalien käsittelyyn monilla eri tekniikan alueilla, kuten telekommunikaatiossa, kuvankäsittelyssä ja lääketieteellisissä laitteissa. Ne ovat niin yleisiä, että insinöörit käyttävät paljon aikaa ja resursseja niiden toteuttamiseen ja verifioimiseen. Koska yleisimpien suotimien rakenne on melko yksinkertainen, niiden luominen voidaan automatisoida generaattorin avulla. Tässä diplomityössä Nokia Networksin vaatimukset kartoitetaan automatisoidun suodinten laitteistokuvauksen tuottamisvuon kehittämiseksi. Erilaisia tuottamismenetelmiä vertaillaan, mutta lopulta päädytään kehittämään oma generaattori. Se luo suotimia yhdistelemällä osia käsinkirjoitetusta RTL:stä. Lopputuloksena on automatisoitu vuo, joka tukee vakiokertoimilla varustettuja, yhden tai useamman kanavan FIR-suotimia. Käyttäjän tulee syöttää kertoimet ja haluttu datanleveys Matlab-skriptiin. Ajettaessa skripti luo suotimen ja verifioi sen. Vuo tukee sekä ASIC- että FPGA-teknologioita.Digital filters are used to process signals in many fields like telecommunications, image processing and in medical equipment. They are so omnipresent that engineers are building and verifying those all the time, using a lot of resources. As the structure of a basic filter is quite simple, savings could be made by automatizing the creation of filters. In this Thesis the requirements of Nokia Networks are analyzed to build an automatized filter generation flow. Different tools are evaluated, but finally a custom generator is built. It crafts filters from pieces of hand-written RTL. The end result is an automated flow which supports single and multichannel FIR filters with constant coefficients. The user has to input the coefficients to a Matlab script with the desired data widths. The filter is then generated and verified by running the script. The flow supports both ASIC and FPGA technologies