State of the art baseband DSP platforms for Software Defined Radio: A survey

Software Defined Radio (SDR) is an innovative approach which is becoming a more and more promising technology for future mobile handsets. Several proposals in the field of embedded systems have been introduced by different universities and industries to support SDR applications. This article presents an overview of current platforms and analyzes the related architectural choices, the current issues in SDR, as well as potential future trends.Peer reviewe

Research on Implementation of Rake Receiver and Cell Search Algorithm for WCDMA System

本论文主要研究WCDMA系统中移动终端侧的下行链路Rake接收机以及小区搜索算法的SystemC仿真及其ASIC实现。 Rake接收机的功能就是完成多径分离合并，从而有效克服多径衰落对移动通信系统性能产生的严重影响。W-CDMA具有很高的码片速率，因此具有很强的多径分辨能力。本文根据WCDMA系统的物理层技术特点，首先详细分析了导频辅助相干(PSAC)Rake接收机的算法实现方案，然后在系统仿真软件CoCentric下按照3GPP的测试规范进行了链路级仿真。 小区搜索是WCDMA物理层另一项关键技术。辅助同步码序号识别过程是小区搜索第二阶段的核心。本文提出了一种PSACRake结构辅同步码...This thesis deals with the study of Cell searcher，as well as downlink PSAC Rake receiver’s algorithm，and its SystemC simulation and ASIC implementation for W-CDMA Mobile terminal. Rake receiver is a well-known technique for resolving and combining multipath signals in DS-CDMA systems which can improve system performance significantly by suppressing the effect multipath fading. Since WCDMA syst...学位：理学硕士院系专业：计算机与信息工程学院电子工程系_无线电物理学号：20013000

A wave pipeline-based WCDMA multipath searcher for a high speed operation

The multiplexing technique of the Wideband-Code Division Multiple Access (WCDMA) is widely applied in the third generation (3G) of cellular systems. The WCDMA uses scrambling codes to differentiate the mobile terminals. In a channel, multipaths may occur when the transmitted signal is reflected from objects in the receiver's environment, so that multiple copies of the signal arrive at the antenna at different moments. Thus, a wideband signal may suffer frequency selective fading due to the multipath propagations. A Rake receiver is often used to combine the energies received on different paths, and a multipath searcher is needed to identify the multipath components and their associated delays. Correlating some shifted versions of the scrambling code with an incoming signal results in energy peaks at the multipath locations, when the locally generated scrambling sequence is aligned with the scrambling sequence of the incoming signal. A path acquisition in such a process requires a speed of millions of Multiply-Accumulate (MAC) cycles per second. The performances of the multipath searcher are mainly determined by the resolution and the acquisition time, which are often limited by the operation speed of the hardware resources. This thesis presents the design of a multipath searcher with a high resolution and a short acquisition time. The design consists of two aspects. The first aspect is of the searching algorithm. It is based on a double-dwell algorithm and a verification stage is introduced to lower the rate of false alarms. The second aspect in the design is the circuit of the searcher. This circuit is expected to operate at the chip rate of 3.84 MHz and the search period is chosen to be equal to the time interval of 5 slots, which requires a high operation speed of the computation units employed in the circuit. Moreover, in order to reduce the circuit complexity, only one Complex Multiplier-Accumulator (CMAC), instead of several ones in many existing searcher circuits, is employed to perform all the computation tasks without extending the search period, which make the computation time in the circuit more critical. Aiming at this challenge of the high speed requirement, a structure of the CMAC cell is designed with the technique of the wave pipeline, which permits the signal propagation through the circuit stages without constraints of clocks. For a good use of this technique, the circuit blocks are made to have equalized delay, by means of pass transistor logic cells, and by keeping such a delay short, the total computation time of the CMAC can be made within the required time limit of the searching. A complete circuit of the CMAC has been developed. It has two versions, with the Normal Process Complementary Pass Logic (NPCPL) and the Complementary Pass-Logic Transmission-Gates (CPL-TG), respectively. The structures of the arithmetic units have been chosen carefully so that the fan-in/fan-out constraints of the NPCPL and the CPL-TG logics are taken into consideration. The results of the simulation with a 0.18 om models have shown that this wave pipelined CMAC can process four inputs of 8 bits at a rate of 830 Mb/s. In order to evaluate the effectiveness of the searching algorithm, a Matlab simulation of the searcher circuit has been conducted. It has been observed that the proposed multipath searcher can lead to low probabilities of misdetection and false alarm for the test cases recommended by the 3 rd Generation Partnership Project (3GPP) standard. A test chip of the CMAC circuit has been fabricated in a CMOS 0.18 om technology process. The circuit is currently under test

Digital Power Detector for WCDMA Transmitter

A 3G mobile phone must have the ability to control its output power with high precision. A power detector is used to measure the actual power outputted by the power amplifier to the antenna. With higher data rates the traditional implementations with peak detectors have become very difficult to use, which is why true RMS detectors are needed. In this thesis the digital part of a true RMS detector for W-CDMA has been designed. The analog parts of the power detector form a quadrature demodulator that transforms the radio signal down to DC where it is occupies a band from 0 to 2 MHz. The measured power amplifier output signal is sampled at 1 MHz which prohibits direct calculation of the RMS voltage in the detector. Instead the detector uses the wave form generator output as a reference to determine the amplification in the transmitter chain which can then be used to find the output power (wave form generator output has constant known power). This requires time alignment of the two signals which is done using a least mean square method of correlation. Using the reference up-sampled to 104 MHz allows very good accuracy despite the low sample rate of the power amplifier signal. To overcome distortion in the power amplifier an additional distortion reducing algorithm has been developed. An estimate of the output power can be delivered after 100 μs and has a standard deviation of its error of 0.05 dB. The error from changing modulation type is limited to a maximum 0.04 dB, well below the specified 0.1 dB. The solution is accurate and modulation independent

Design and Implementation of Software Defined Radios on a Homogeneous Multi-Processor Architecture

In the wireless communications domain, multi-mode and multi-standard platforms are becoming increasingly the central focus of system architects. In fact, mobile terminal users require more and more mobility and throughput, pushing towards a fully integrated radio system able to support different communication protocols running concurrently on the platform. A new concept of radio system was introduced to meet the users' expectations. Flexible radio platforms have became an indispensable requirement to meet the expectations of the users today and in the future. This thesis deals with issues related to the design of flexible radio platforms. In particular, the flexibility of the radio system is achieved through the concept of software defined radios (SDRs). The research work focuses on the utilization of homogeneous multi-processor (MP) architectures as a feasible way to efficiently implement SDR platforms. In fact, platforms based on MP architectures are able to deliver high performance together with a high degree of flexibility. Moreover, homogeneous MP platforms are able to reduce design and verification costs as well as provide a high scalability in terms of software and hardware. However, homogeneous MP architectures provide less computational efficiency when compared to heterogeneous solutions. This thesis can be divided into two parts: the first part is related to the implementation of a reference platform while the second part of the thesis introduces the design and implementation of flexible, high performance, power and energy efficient algorithms for wireless communications. The proposed reference platform, Ninesilica, is a homogeneous MP architecture composed of a 3x3 mesh of processing nodes (PNs), interconnected by a hierarchical Network-on-Chip (NoC). Each PN hosts as Processing Element (PE) a processor core. To improve the computational efficiency of the platform, different power and energy saving techniques have been investigated. In the design, implementation and mapping of the algorithms, the following constraints were considered: energy and power efficiency, high scalability of the platform, portability of the solutions across similar platforms, and parallelization efficiency. Ninesilica architecture together with the proposed algorithm implementations showed that homogeneous MP architectures are highly scalable platforms, both in terms of hardware and software. Furthermore, Ninesilica architecture demonstrated that homogeneous MPs are able to achieve high parallelization efficiency as well as high energy and power savings, meeting the requirements of SDRs as well as enabling cognitive radios. Ninesilica can be utilized as a stand-alone block or as an elementary building block to realize clustered many-core architectures. Moreover, the obtained results, in terms of parallelization efficiency as well as power and energy efficiency are independent of the type of PE utilized, ensuring the portability of the results to similar architectures based on a different type of processing element