Efficient Hardware Implementation of Probabilistic Gradient Descent Bit Flipping

This paper presents a new Bit Flipping (BF) decoder, called Probabilistic Parallel Bit Flipping (PPBF) for Low-Density Parity-Check (LDPC) codes on the Binary Symmetric Channel. In PPBF, the flipping operation is preceded with a probabilistic behavior which is shown to improve significantly the error correction performance. The advantage of PPBF comes from the fact that, no global computation is required during the decoding process and from that, all the computations can be executed in the local computing units and in-parallel. PPBF provides a considerable improvement of the decoding frequency and complexity, compared to other known BF decoders, while obtaining a significant gain in error correction. One improved version of PPBF, called non-syndrome PPBF (NS-PPBF) is also introduced, in which the global syndrome check is moved out of the critical path and a new terminating mechanism is proposed. In order to show the superiority of the new decoders in terms of hardware efficiency and decoding throughput, the corresponding hardware architectures are presented in the second part of the paper. The ASIC synthesis results confirm that, the decoding frequency of the proposed decoders is significantly improved, much higher than the BF decoders of literature while requiring lower complexity to be efficiently implemented

Low-Power 400-Gbps Soft-Decision LDPC FEC for Optical Transport Networks

We present forward error correction systems based on soft-decision low-density parity check (LDPC) codes for applications in 100–400-Gbps optical transport networks. These systems are based on the low-complexity “adaptive degeneration” decoding algorithm, which we introduce in this paper, along with randomly-structured LDPC codes with block lengths from 30 000 to 60 000 bits and overhead (OH) from 6.7% to 33%. We also construct a 3600-bit prototype LDPC code with 20% overhead, and experimentally show that it has no error floor above a bit error rate (BER) of 10−15 using a field-programmable gate array (FPGA)-based hardware emulator. The projected net coding gain at a BER of 10−15 ranges from 9.6 dB at 6.7% OH to 11.2 dB at 33% OH. We also present application-specific integrated circuit synthesis results for these decoders in 28 nm fully depleted silicon on insulator technology, which show that they are capable of 400-Gbps operation with energy consumption of under 3 pJ per information bit

Flexible encoder and decoder of low density parity check codes

У дисертацији су предложена брза, флексибилна и хардверски ефикасна решења за кодовање и декодовање изузетно нерегуларних кодова са проверама парности мале густине (енгл. low-density parity-check, LDPC, codes) захтевана у савременим комуникационим стандардима. Један део доприноса дисертације је у новој делимично паралелној архитектури LDPC кодера за пету генерацију мобилних комуникација. Архитектура је заснована на флексибилној мрежи за кружни померај која омогућава паралелно процесирање више делова контролне матрице кратких кодова чиме се остварује сличан ниво паралелизма као и при кодовању дугачких кодова. Поред архитектуралног решења, предложена је оптимизација редоследа процесирања контролне матрице заснована на генетичком алгоритму, која омогућава постизање великих протока, малог кашњења и тренутно најбоље ефикасности искоришћења хардверских ресурса. У другом делу дисертације предложено је ново алгоритамско и архитектурално решење за декодовање структурираних LDPC кодова. Често коришћени приступ у LDPC декодерима је слојевито декодовање, код кога се услед проточне обраде јављају хазарди података који смањују проток. Декодер предложен у дисертацији у конфликтним ситуацијама на погодан начин комбинује слојевито и симултано декодовање чиме се избегавају циклуси паузе изазвани хазардима података. Овај приступ даје могућност за увођење великог броја степени проточне обраде чиме се постиже висока учестаност сигнала такта. Додатно, редослед процесирања контролне матрице је оптимизован коришћењем генетичког алгоритма за побољшане перформансе контроле грешака. Остварени резултати показују да, у поређењу са референтним решењима, предложени декодер остварује значајна побољшања у протоку и најбољу ефикасност за исте перформансе контроле грешака.The dissertation proposes high speed, flexible and hardware efficient solutions for coding and decoding of highly irregular low-density parity-check (LDPC) codes, required by many modern communication standards. The first part of the dissertation’s contributions is in the novel partially parallel LDPC encoder architecture for 5G. The architecture was built around the flexible shifting network that enables parallel processing of multiple parity check matrix elements for short to medium code lengths, thus providing almost the same level of parallelism as for long code encoding. In addition, the processing schedule was optimized for minimal encoding time using the genetic algorithm. The optimization procedure contributes to achieving high throughputs, low latency, and up to date the best hardware usage efficiency (HUE). The second part proposes a new algorithmic and architectural solution for structured LDPC code decoding. A widely used approach in LDPC decoders is a layered decoding schedule, which frequently suffers from pipeline data hazards that reduce the throughput. The decoder proposed in the dissertation conveniently incorporates both the layered and the flooding schedules in cases when hazards occur and thus facilitates LDPC decoding without stall cycles caused by pipeline hazards. Therefore, the proposed architecture enables insertion of many pipeline stages, which consequently provides a high operating clock frequency. Additionally, the decoding schedule was optimized for better signal-to-noise ratio (SNR) performance using genetic algorithm. The obtained results show that the proposed decoder achieves great throughput increase and the best HUE when compared with the state of the art for the same SNR performance