Concurrency reduction of untimed latch protocols - theory and practice

Journal ArticleA systematic investigation into concurrency reduction of untimed asynchronous 4-phase latch controllers is reported. Starting with a state graph that exhibits maximal concurrency, rules are provided for systematically reducing its states and thereby curtailing its behaviors. The rules predict liveness and occupancy, as well as the regularity and behavior of their pipelines. The rules also reveal the precise extent of the design space and thus provide a secure platform on which to study the implications of concurrency reduction on power, performance and area by implementing and evaluating the complete set of abstracted controllers. This complete characterization enhances the understanding and usage of concurrency and its reduction in handshake protocols. Trade-offs have been observed and reported which will aid designers in trying to find the best protocols for a required specification. Finally, the best synthesized protocols in this class have been identified

Circuiti asincroni: dai principi fondamentali all'implementazione

La maggioranza dei circuiti commercializzati al giorno d'oggi è di tipo sincrono. Negli ultimi anni però, questa tecnologia si è trovata a dover affrontare notevoli problemi legati al consumo di potenza e alle crescenti difficoltà di gestione del clock, in circuiti sempre più piccoli e densi. Per ovviare a queste problematiche, che richiedono soluzioni tecnicamente complesse e dispendiose, i costruttori stanno portando l'attenzione sull'approccio asincrono che, privo di clock, promette di ridurre i consumi e velocizzare i circuiti. La mancanza di esperienza, strumenti e motivazioni adeguate rende però molto difficile una migrazione totale da un paradigma all'altro. La tecnologia che sembra destinata a prendere piede in questo contesto è quindi l'approccio ibrido Globally Asynchronous, Locally Synchronous. Importanti produttori sono impegnati nella ricerca in questo settore, che è ancora in piena fase evolutiva. Il presente lavoro è diviso in due parti: nella prima offriremo un quadro generale sui fondamenti della tecnologia asincrona e, nella seconda, vedremo esempi di design che rappresentano l'attuale stato dell'arteope

Gate and Throughput Optimizations for NULL Convention Self-timed Digital Circuits

NULL Convention Logic (NCL) provides an asynchronous design methodology employing dual-rail signals, quad-rail signals, or other Mutually Exclusive Assertion Groups (MEAGs) to incorporate data and control information into one mixed path. In NCL, the control is inherently present with each datum, so there is no need for worse-case delay analysis and control path delay matching. This dissertation focuses on optimization methods for NCL circuits, specifically addressing three related architectural areas of NCL design. First, a design method for optimizing NCL circuits is developed. The method utilizes conventional Boolean minimization followed by table-driven gate substitutions. It is applied to design time and space optimal fundamental logic functions, a time and space optimal full adder, and time, transistor count, and power optimal up-counter circuits. The method is applicable when composing logic functions where each gate is a state-holding element; and can produce delay-insensitive circuits requiring less area and fewer gate delays than alternative gate-level approaches requiring full minterm generation. Second, a pipelining method for producing throughput optimal NCL systems is developed. A relationship between the number of gate delays per stage and the worse-case throughput for a pipeline as a whole is derived. The method then uses this relationship to minimize a pipeline\u27s worse-case throughput by partitioning the NCL combinational circuitry through the addition of asynchronous registers. The method is applied to design a maximum throughput unsigned multiplier, which yields a speedup of 2.25 over the non-pipelined version, while maintaining delay-insensitivity. Third, a technique to mitigate the impact of the NULL cycle is developed. The technique further increases the maximum attainable throughput of a NCL system by reducing inherent overheads associated with an integrated data and control path. This technique is applied to a non-pipelined 4-bit by 4-bit unsigned multiplier to yield a speedup of 1.61 over the standalone version. Finally, these techniques are applied to design a 72+32x32 multiply and accumulate (MAC) unit, which outperforms other delay-insensitive/self-timed MACs in the literature. It also performs conditional rounding, scaling, and saturation of the output, whereas the others do not; thus further distinguishing it from the previous work. The methods developed facilitate speed, transistor count, and power tradeoffs using approaches that are readily automatable