High Linearity Millimeter Wave Power Amplifiers with Novel Linearizer Techniques

Millimeter-wave communications have experienced phenomenal growth in recent years when limited frequency spectrum is occupied by the ever-developing communication services. The power amplifier, as the key component in the transmitter/receiver module of communication systems, affects performance of the whole system directly and receives much attention. For minimized distortion and optimum system performance, the non-constant en- velope modulation schemes used in communication systems have challenging requirements on linearity. As linearity is related to communication quality directly, several linearization techniques, such as predistortion and feedforward, are applied to power amplifier design. Predistortion method has the advantages over other techniques in relatively simple struc- ture and reasonable linearity improvement. But current predistortion circuits have quite limited performance improvement and relatively large insertion loss, which indicate the need for further research. In most of millimeter-wave amplifier design, great effort has been spent on output power or gain, while linearity is often ignored. As almost all the predistortion circuits operate at the RF frequencies, the linearized millimeter-wave com- munication circuit is still relatively immature and very challenging. This project is dedicated to solve the linearity problem faced by millimeter-wave power amplifier in communication systems, which lacks of e®ective techniques in this field. Linearity improvement with the predistortion method will be the key issue in this project and some original ideas for predistortion circuit design will be applied to millimeter-wave amplifiers. In this thesis, several predistortion circuits with novel structure were proposed, which provide a new approach for linearity improvement for millimeter-wave power am- plifier. A millimeter-wave power ampli¯er for LMDS applications built on GaAs pHEMT technology was developed to a high engineering standard, which works as the test bench for linearization. Actual operation and parasitic elements at tens of gigahertz have been taken into consideration during the design. Firstly, two novel predistorter structures based on the amplifier were proposed, one is based on an amplifier with a fixed bias circuit and the other is based on an amplifier with a nonlinear signal dependant bias circuit. These novel structures can improve the linearity while improving other metrics simultaneously, which can effectively solve the problem of insertion loss faced by the conventional structures. Besides this, an original predistortion circuit design methodology derived from frequency to signal amplitude transformation was proposed. Based on this methodology, several transfer functions were proposed and related predistortion circuits were built to linearize the power amplifier. As this methodology is quite different from the traditional approach, it can improve the linearity signifficantly while other metrics are affected slightly and has a broad prospect for application

High Linearity Millimeter Wave Power Amplifiers with Novel Linearizer Techniques

Millimeter-wave communications have experienced phenomenal growth in recent years when limited frequency spectrum is occupied by the ever-developing communication services. The power amplifier, as the key component in the transmitter/receiver module of communication systems, affects performance of the whole system directly and receives much attention. For minimized distortion and optimum system performance, the non-constant en- velope modulation schemes used in communication systems have challenging requirements on linearity. As linearity is related to communication quality directly, several linearization techniques, such as predistortion and feedforward, are applied to power amplifier design. Predistortion method has the advantages over other techniques in relatively simple struc- ture and reasonable linearity improvement. But current predistortion circuits have quite limited performance improvement and relatively large insertion loss, which indicate the need for further research. In most of millimeter-wave amplifier design, great effort has been spent on output power or gain, while linearity is often ignored. As almost all the predistortion circuits operate at the RF frequencies, the linearized millimeter-wave com- munication circuit is still relatively immature and very challenging. This project is dedicated to solve the linearity problem faced by millimeter-wave power amplifier in communication systems, which lacks of e®ective techniques in this field. Linearity improvement with the predistortion method will be the key issue in this project and some original ideas for predistortion circuit design will be applied to millimeter-wave amplifiers. In this thesis, several predistortion circuits with novel structure were proposed, which provide a new approach for linearity improvement for millimeter-wave power am- plifier. A millimeter-wave power ampli¯er for LMDS applications built on GaAs pHEMT technology was developed to a high engineering standard, which works as the test bench for linearization. Actual operation and parasitic elements at tens of gigahertz have been taken into consideration during the design. Firstly, two novel predistorter structures based on the amplifier were proposed, one is based on an amplifier with a fixed bias circuit and the other is based on an amplifier with a nonlinear signal dependant bias circuit. These novel structures can improve the linearity while improving other metrics simultaneously, which can effectively solve the problem of insertion loss faced by the conventional structures. Besides this, an original predistortion circuit design methodology derived from frequency to signal amplitude transformation was proposed. Based on this methodology, several transfer functions were proposed and related predistortion circuits were built to linearize the power amplifier. As this methodology is quite different from the traditional approach, it can improve the linearity signifficantly while other metrics are affected slightly and has a broad prospect for application

Design and implementation of an ETSI-SDR OFDM transmitter with power amplifier linearizer

Satellite radio has attained great popularity because of its wide range of geographical coverage and high signal quality as compared to the terrestrial broadcasts. Most Satellite Digital Radio (SDR) based systems favor multi-carrier transmission schemes, especially, orthogonal frequency division multiplexing (OFDM) transmission because of high data transfer rate and spectral efficiency. It is a challenging task to find a suitable platform that supports fast data rates and superior processing capabilities required for the development and deployment of the new SDR standards. Field programmable gate array (FPGA) devices have the potential to become suitable development platform for such standards. Another challenging factor in SDR systems is the distortion of variable envelope signals used in OFDM transmission by the nonlinear RF power amplifiers (PA) used in the base station transmitters. An attractive option is to use a linearizer that would compensate for the nonlinear effects of the PA. In this research, an OFDM transmitter, according to European Telecommunications Standard Institute (ETSI) SDR Technical Specifications 2007-2008, was designed and implemented on a low-cost Xilinx FPGA platform. A weakly nonlinear PA, operating in the L-band SDR frequency (1.450-1.490GHz), was used for signal transmission. An FPGA-based, low-cost, adaptive linearizer was designed and implemented based on the digital predistortion (DPD) reference design from Xilinx, to correct the distortion effects of the PA on the transmitted signal

Design of analog predistorter

Abstract. In this thesis, two analog predistorter circuits are designed for linearizing the CMOS power amplifier in MIMO transceivers. The first circuit uses two parallel transistors as conventional derivative superposition, where derivatives of the transistor drain currents are biased to have opposite phases for 3rd-order distortion components. This results in the cancellation and thus providing a very linear 3rd-order response. The other design, using complementary derivative superposition topology, has p- and n-type transistors with a common drain self-biasing to achieve expansive power gain. This is used to improve the 1-dB compression point of the CMOS power amplifier. Simulation results of conventional derivative superposition circuit show over 25 dB improvement in distortion level, while still providing a fair amount of power gain. Implementation with a CMOS power amplifier shows a 2.6 dB improvement in 1 dB compression point. With the circuit having expansive characteristics, adjustable gain-expansion behaviour is achieved. With the implemented digital bias control, expansion between 2.5 dB and 4 dB is achieved, with gain variation between -2.4 dB and 1 dB. With a CMOS power amplifier, 3.5 dB improvement in 1 dB compression point is achieved, allowing the power amplifier to be used with greater efficiency. Both circuits are implemented using 22nm CMOS SOI technology and submitted to fabrication

A fast engineering approach to high efficiency power amplifier linearization for avionics applications

This PhD thesis provides a fast engineering approach to the design of digital predistortion (DPD) linearizers from several perspectives: i) enhancing the off-line training performance of open-loop DPD, ii) providing robustness and reducing the computational complexity of the parameters identification subsystem and, iii) importing machine learning techniques to favor the automatic tuning of power amplifiers (PAs) and DPD linearizers with several free-parameters to maximize power efficiency while meeting the linearity specifications. One of the essential parts of unmanned aerial vehicles (UAV) is the avionics, being the radio control one of the earliest avionics present in the UAV. Unlike the control signal, for transferring user data (such as images, video, etc.) real-time from the drone to the ground station, large transmission rates are required. The PA is a key element in the transmitter chain to guarantee the data transmission (video, photo, etc.) over a long range from the ground station. The more linear output power, the better the coverage or alternatively, with the same coverage, better SNR allows the use of high-order modulation schemes and thus higher transmission rates are achieved. In the context of UAV wireless communications, the power consumption, size and weight of the payload is of significant importance. Therefore, the PA design has to take into account the compromise among bandwidth, output power, linearity and power efficiency (very critical in battery-supplied devices). The PA can be designed to maximize its power efficiency or its linearity, but not both. Therefore, a way to deal with this inherent trade-off is to design high efficient amplification topologies and let the PA linearizers take care of the linearity requirements. Among the linearizers, DPD linearization is the preferred solution to both academia and industry, for its high flexibility and linearization performance. In order to save as many computational and power resources as possible, the implementation of an open-loop DPD results a very attractive solution for UAV applications. This thesis contributes to the PA linearization, especially on off-line training for open-loop DPD, by presenting two different methods for reducing the design and operating costs of an open-loop DPD, based on the analysis of the DPD function. The first method focuses on the input domain analysis, proposing mesh-selecting (MeS) methods to accurately select the proper samples for a computationally efficient DPD parameter estimation. Focusing in the MeS method with better performance, the memory I-Q MeS method is combined with feature extraction dimensionality reduction technique to allow a computational complexity reduction in the identification subsystem by a factor of 65, in comparison to using the classical QR-LS solver and consecutive samples selection. In addition, the memory I-Q MeS method has been proved to be of crucial interest when training artificial neural networks (ANN) for DPD purposes, by significantly reducing the ANN training time. The second method involves the use of machine learning techniques in the DPD design procedure to enlarge the capacity of the DPD algorithm when considering a high number of free parameters to tune. On the one hand, the adaLIPO global optimization algorithm is used to find the best parameter configuration of a generalized memory polynomial behavioral model for DPD. On the other hand, a methodology to conduct a global optimization search is proposed to find the optimum values of a set of key circuit and system level parameters, that properly combined with DPD linearization and crest factor reduction techniques, can exploit at best dual-input PAs in terms of maximizing power efficiency along wide bandwidths while being compliant with the linearity specifications. The advantages of these proposed techniques have been validated through experimental tests and the obtained results are analyzed and discussed along this thesis.Aquesta tesi doctoral proporciona unes pautes per al disseny de linealitzadors basats en predistorsió digital (DPD) des de diverses perspectives: i) millorar el rendiment del DPD en llaç obert, ii) proporcionar robustesa i reduir la complexitat computacional del subsistema d'identificació de paràmetres i, iii) incorporació de tècniques d'aprenentatge automàtic per afavorir l'auto-ajustament d'amplificadors de potència (PAs) i linealitzadors DPD amb diversos graus de llibertat per poder maximitzar l’eficiència energètica i al mateix temps acomplir amb les especificacions de linealitat. Una de les parts essencials dels vehicles aeris no tripulats (UAV) _es l’aviònica, sent el radiocontrol un dels primers sistemes presents als UAV. Per transferir dades d'usuari (com ara imatges, vídeo, etc.) en temps real des del dron a l’estació terrestre, es requereixen taxes de transmissió grans. El PA _es un element clau de la cadena del transmissor per poder garantir la transmissió de dades a grans distàncies de l’estació terrestre. A major potència de sortida, més cobertura o, alternativament, amb la mateixa cobertura, millor relació senyal-soroll (SNR) la qual cosa permet l’ús d'esquemes de modulació d'ordres superiors i, per tant, aconseguir velocitats de transmissió més altes. En el context de les comunicacions sense fils en UAVs, el consum de potència, la mida i el pes de la càrrega útil són de vital importància. Per tant, el disseny del PA ha de tenir en compte el compromís entre ample de banda, potència de sortida, linealitat i eficiència energètica (molt crític en dispositius alimentats amb bateries). El PA es pot dissenyar per maximitzar la seva eficiència energètica o la seva linealitat, però no totes dues. Per tant, per afrontar aquest compromís s'utilitzen topologies amplificadores d'alta eficiència i es deixa que el linealitzador s'encarregui de garantir els nivells necessaris de linealitat. Entre els linealitzadors, la linealització DPD és la solució preferida tant per al món acadèmic com per a la indústria, per la seva alta flexibilitat i rendiment. Per tal d'estalviar tant recursos computacionals com consum de potència, la implementació d'un DPD en lla_c obert resulta una solució molt atractiva per a les aplicacions UAV. Aquesta tesi contribueix a la linealització del PA, especialment a l'entrenament fora de línia de linealitzadors DPD en llaç obert, presentant dos mètodes diferents per reduir el cost computacional i augmentar la fiabilitat dels DPDs en llaç obert. El primer mètode se centra en l’anàlisi de l’estadística del senyal d'entrada, proposant mètodes de selecció de malla (MeS) per seleccionar les mostres més significatives per a una estimació computacionalment eficient dels paràmetres del DPD. El mètode proposat IQ MeS amb memòria es pot combinar amb tècniques de reducció del model del DPD i d'aquesta manera poder aconseguir una reducció de la complexitat computacional en el subsistema d’identificació per un factor de 65, en comparació amb l’ús de l'algoritme clàssic QR-LS i selecció de mostres d'entrenament consecutives. El segon mètode consisteix en l’ús de tècniques d'aprenentatge automàtic pel disseny del DPD quan es considera un gran nombre de graus de llibertat (paràmetres) per sintonitzar. D'una banda, l'algorisme d’optimització global adaLIPO s'utilitza per trobar la millor configuració de paràmetres d'un model polinomial amb memòria generalitzat per a DPD. D'altra banda, es proposa una estratègia per l’optimització global d'un conjunt de paràmetres clau per al disseny a nivell de circuit i sistema, que combinats amb linealització DPD i les tècniques de reducció del factor de cresta, poden maximitzar l’eficiència de PAs d'entrada dual de gran ample de banda, alhora que compleixen les especificacions de linealitat. Els avantatges d'aquestes tècniques proposades s'han validat mitjançant proves experimentals i els resultats obtinguts s'analitzen i es discuteixen al llarg d'aquesta tesi

Intermodulation distortion performance enhancement of microwave power amplifiers

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.This thesis reports the author's investigation of the effects of the injection of specific signals on the intermodulation distortion performance of microwave power amplifiers. Theory, simulation and practical results are presented, analysed and compared. The thesis gives the reader background knowledge of power amplifiers and their nonlinearities and go on to analyse the phenomena of intermodulation distortion product generation in power amplifiers. The analysis is based on a three-tone test since this highlights a second kind of third order intermodulation distortion (IMD3), which are in general higher in amplitude than the first kind of IMD3 found in a two-tone test. A mathematical analysis and a simulation of a MESFET amplifier are performed. It enables the comparison of the performance of IMD cancellation by injection of signals whose frequencies are chosen to be first, the second harmonic of the fundamental signals, second, the sum of the fundamental signal frequencies and finally the difference frequencies of the fundamental signals. A practical implementation of the difference frequency technique is then presented and practical results are compared to the other two techniques of second harmonic injection and the injection of the sum of fundamental frequencies. It is further shown that in practise these two techniques may be considered as a single technique

Mitigation of Memory Effects in High Power Microwave Amplifiers

This thesis expounds on the application of Doherty Power Amplifiers (DPA) along with baseband Digital PreDistortion (DPD) techniques to tackle the antagonistic demands of high power efficiency and linearity imposed by modern communications. Memoryless modeling is firstly introduced and its limitations when dealing with PAs driven with realistic devices. Therefore, electrical memory effects are explored in greater detail and a mathematical model showing the relation between the various harmonic components in the output and how they can re-mix back into the fundamental band is developed. The importance of the output bias network in the reduction of memory effects is highlighted. A memory polynomial (MP) based DPD is shown to be a good solution for the linearization of wideband DPA which exhibit strong memory effects. To further improve this solution, the complexity of the MP-DPD is reduced. For that, the even-order terms in the MP branches were first removed. Then, the PA memory effects theory was used to further reduce the number of coefficients of the MP-DPD by decreasing the nonlinearity orders in the different branches individually. These two steps allowed for a reduction of the number of coefficients to almost one-third and the conditioning number by three orders of magnitude while maintaining the same linearization capability. This substantially alleviates the requirements on the digital signal processors and the time needed to construct and implement the MP-DPD in real environment. Experimental validation carried out using a 400 Watt DPA, driven with 4-Carrier WCDMA signal, showed excellent linearization capability by achieving an ACPR of better than 50 dBc with a power efficiency of better than 42.4%. Despite this, the depth of the memory effects in the DPA was still significant. While an effort was made to reduce further the memory effects, the discrepancy between the simulated behavior of the DPA and that observed in simulation was significant. In an attempt to rule out the DPA structure as the cause of the discrepancy between the measured results and the behavior predicted in simulation, a single branch class AB PA was designed using the transistor model. The PA behavior was well predicted when driven with a Continuous Wave (CW) signal, however the simulated and measured behavior differed greatly when the PA was driven by a two tone signal. This rendered the desired reduction of the memory effects impossible at the design stage

High frequency CMOS amplifier with improved linearity

In this paper, a novel amplifier linearisation technique based on the negative impedance compensation is presented. As demonstrated by using Volterra model, the proposed technique is suitable for linearising amplifiers with low open-loop gain, which is appropriate for RF/microwave applications. A single-chip CMOS amplifier has been designed using the proposed method, and the simulation results show that high gain accuracy (improved by 38%) and high linearity (IMD3 improved by 14 dB, OIP3 improved by 11 dB and adjacent channel power ratio (ACPR) improved by 44% for CDMA signal) can be achieved

Transformer NN-based behavioral modeling and predistortion for wideband pas

Abstract. This work investigates the suitability of transformer neural networks (NNs) for behavioral modeling and the predistortion of wideband power amplifiers. We propose an augmented real-valued time delay transformer NN (ARVTDTNN) model based on a transformer encoder that utilizes the multi-head attention mechanism. The inherent parallelized computation nature of transformers enables faster training and inference in the hardware implementation phase. Additionally, transformers have the potential to learn complex nonlinearities and long-term memory effects that will appear in future high-bandwidth power amplifiers. The experimental results based on 100 MHz LDMOS Doherty PA show that the ARVTDTNN model exhibits superior or comparable performance to the state-of-the-art models in terms of normalized mean square error (NMSE) and adjacent channel power ratio (ACPR). It improves the NMSE and ACPR up to −37.6 dB and −41.8 dB, respectively. Moreover, this approach can be considered as a generic framework to solve sequence-to-one regression problems with the transformer architecture

Kalman filtering algorithm for on-line memory polynomial predistortion

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