Design methodology of a modular CMOS ultra-low power self-biased current source

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Engenharia Elétrica, Florianópolis, 2017.Neste documento é desenvolvida uma metodologia de projeto de uma fonte de corrente auto polarizada de ultra baixo consumo de potência em tecnologia CMOS. É descrita uma topologia modular implementada com dois MOSFETs auto cascodados (SCMs) e um amplificador operacional. A metodologia proposta está baseada no conceito de ni´veis de inversão e o espaço de projeto do circuito é descrito principalmente em termos das especificações do amplificador operacional e do espelho de corrente PMOS. O circuito foi projetado usando uma tecnologia padrão CMOS de 130 nm. Os resultados das simulações são apresentados neste documento para validar a metodologia de projeto e o desempenho da fonte de corrente, mostrando que o circuito proposto pode operar com uma tensão de alimentação menor de 1 V e com menos de 1%/V na regulação de linha.Abstract : In this document a design procedure of a CMOS ultra-low-power self-biased current source is developed. A modular topology using two self-cascode MOSFETs (SCMs), a current mirror and an operational amplifier is implemented. The described methodology is based on the concept of inversion level, and the design space of the current source is described mainly in terms of the specifications of the operational amplifier and the PMOS current mirror. The circuit was designed in a 130 nm standard CMOS technology. Simulation results are provided to validate the design methodology and the performance of the current source, showing that the proposed circuit can operate at a supply voltage less than 1 V with less than 1%/V of line regulation

Analog System-on-a-Chip with Application to Biosensors

This dissertation facilitates the design and fabrication of analog systems-on-a-chip (SoCs). In this work an analog SoC is developed with application to organic fluid analysis. The device contains a built-in self-test method for performing on-chip analysis of analog macros. The analog system-on-a-chip developed in this dissertation can be used to evaluate the properties of fluids for medical diagnoses. The research herein described covers the development of: analog SoC models, an improved set of chemical sensor arrays, a self-contained system-on-a-chip for the determination of fluid properties, and a method of performing on-chip testing of analog SoC sub-blocks

MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR

As the device dimensions have reduced from micrometer to nanometer range, new bulk silicon devices are now facing many undesirable effects of scaling leading device engineers to look for new process technologies. Silicon-on-insulator (SOI) has emerged as a very promising candidate for resolving the major problems plaguing the bulk silicon technology. G4FET [G4FET] is a SOI transistor with four independent gates. Although G4FET has already shown great potential in different applications, the widespread adoption of a technology in circuit design is heavily dependent upon good SPICE (Simulation Program with Integrated Circuit Emphasis) models. CAD (Computer Aided Design) tools are now ubiquitous in circuit design and a fast, robust and accurate SPICE model is absolutely necessary to transform G4FET into a mainstream technology. The research goal is to develop suitable SPICE models for G4FET to aid circuit designers in designing innovative analog and digital circuits using this new transistor. The first phase of this work is numerical modeling of the G4FET where four different numerical techniques are implemented, each with its merits and demerits. The first two methods are based on multivariate Lagrange interpolation and multidimensional Bernstein polynomial. The third numerical technique is based on multivariate regression polynomial to aid modeling with dense gridded data. Another suitable alternative namely multidimensional linear and cubic spline interpolation is explored as the fourth numerical modeling approach to solve some of the problems resulting from single polynomial approximation. The next phase of modeling involves developing a macromodel combining already existing SPICE models of MOSFET (metal–oxide–semiconductor field-effect transistor) and JFET (junction-gate field-effect transistor). This model is easy to implement in circuit simulators and provides good results compared to already demonstrated experimental works with innovative G4FET circuits. The final phase of this work involves the development of a physics-based compact model of G4FET with some empirical fitting parameters. A model for depletion-all-around operation is implemented in circuit simulator based on previous work. Another simplified model, combining MOS and JFET action, is implemented in circuit simulator to model the accumulation mode operation of G4FET

Improved transistor-controlled and commutated brushless DC motors for electric vehicle propulsion

The development, design, construction, and testing processes of two electronically (transistor) controlled and commutated permanent magnet brushless dc machine systems, for propulsion of electric vehicles are detailed. One machine system was designed and constructed using samarium cobalt for permanent magnets, which supply the rotor (field) excitation. Meanwhile, the other machine system was designed and constructed with strontium ferrite permanent magnets as the source of rotor (field) excitation. These machine systems were designed for continuous rated power output of 15 hp (11.2 kw), and a peak one minute rated power output of 35 hp (26.1 kw). Both power ratings are for a rated voltage of 115 volts dc, assuming a voltage drop in the source (battery) of about 5 volts. That is, an internal source voltage of 120 volts dc. Machine-power conditioner system computer-aided simulations were used extensively in the design process. These simulations relied heavily on the magnetic field analysis in these machines using the method of finite elements, as well as methods of modeling of the machine power conditioner system dynamic interaction. These simulation processes are detailed. Testing revealed that typical machine system efficiencies at 15 hp (11.2 kw) were about 88% and 84% for the samarium cobalt and strontium ferrite based machine systems, respectively. Both systems met the peak one minute rating of 35 hp

Design and Control of Power Converters for High Power-Quality Interface with Utility and Aviation Grids

Power electronics as a subject integrating power devices, electric and electronic circuits, control, and thermal and mechanic design, requires not only knowledge and engineering insight for each subarea, but also understanding of interface issues when incorporating these different areas into high performance converter design.Addressing these fundamental questions, the dissertation studies design and control issues in three types of power converters applied in low-frequency high-power transmission, medium-frequency converter emulated grid, and high-frequency high-density aviation grid, respectively, with the focus on discovering, understanding, and mitigating interface issues to improve power quality and converter performance, and to reduce the noise emission.For hybrid ac/dc power transmission,• Analyze the interface transformer saturation issue between ac and dc power flow under line unbalances.• Proposed both passive transformer design and active hybrid-line-impedance-conditioner to suppress this issue.For transmission line emulator,• Propose general transmission line emulation schemes with extension capability.• Analyze and actively suppress the effects of sensing/sampling bias and PWM ripple on emulation considering interfaced grid impedance.• Analyze the stability issue caused by interaction of the emulator and its interfaced impedance. A criterion that determines the stability and impedance boundary of the emulator is proposed.For aircraft battery charger,• Investigate architectures for dual-input and dual-output battery charger, and a three-level integrated topology using GaN devices is proposed to achieve high density.• Identify and analyze the mechanisms and impacts of high switching frequency, di/dt, dv/dt on sensing and power quality control; mitigate solutions are proposed.• Model and compensate the distortion due to charging transition of device junction capacitances in three-level converters.• Find the previously overlooked device junction capacitance of the nonactive devices in three-level converters, and analyze the impacts on switching loss, device stress, and current distortion. A loss calculation method is proposed using the data from the conventional double pulse tester.• Establish fundamental knowledge on performance degradation of EMI filters. The impacts and mechanisms of both inductive and capacitive coupling on different filter structures are understood. Characterization methodology including measuring, modeling, and prediction of filter insertion loss is proposed. Mitigation solutions are proposed to reduce inter-component coupling and self-parasitics

Adiabatic Approach for Low-Power Passive Near Field Communication Systems

This thesis tackles the need of ultra-low power electronics in the power limited passive Near Field Communication (NFC) systems. One of the techniques that has proven the potential of delivering low power operation is the Adiabatic Logic Technique. However, the low power benefits of the adiabatic circuits come with the challenges due to the absence of single opinion on the most energy efficient adiabatic logic family which constitute appropriate trade-offs between computation time, area and complexity based on the circuit and the power-clocking schemes. Therefore, five energy efficient adiabatic logic families working in single-phase, 2-phase and 4-phase power-clocking schemes were chosen. Since flip-flops are the basic building blocks of any sequential circuit and the existing flip-flops are MUX-based (having more transistors) design, therefore a novel single-phase, 2-phase and 4-phase reset based flip-flops were proposed. The performance of the multi-phase adiabatic families was evaluated and compared based on the design examples such as 2-bit ring counter, 3-bit Up-Down counter and 16-bit Cyclic Redundancy Check (CRC) circuit (benchmark circuit) based on ISO 14443-3A standard. Several trade-offs, design rules, and an appropriate range for the supply voltage scaling for multi-phase adiabatic logic are proposed. Furthermore, based on the NFC standard (ISO 14443-3A), data is frequently encoded using Manchester coding technique before transmitting it to the reader. Therefore, if Manchester encoding can be implemented using adiabatic logic technique, energy benefits are expected. However, adiabatic implementation of Manchester encoding presents a challenge. Therefore, a novel method for implementing Manchester encoding using adiabatic logic is proposed overcoming the challenges arising due to the AC power-clock. Other challenges that come with the dynamic nature of the adiabatic gates and the complexity of the 4-phase power-clocking scheme is in synchronizing the power-clock v phases and the time spent in designing, validation and debugging of errors. This requires a specific modelling approach to describe the adiabatic logic behaviour at the higher level of abstraction. However, describing adiabatic logic behaviour using Hardware Description Languages (HDLs) is a challenging problem due to the requirement of modelling the AC power-clock and the dual-rail inputs and outputs. Therefore, a VHDL-based modelling approach for the 4-phase adiabatic logic technique is developed for functional simulation, precise timing analysis and as an improvement over the previously described approaches

Electrothermal simulation and characterisation of series connected power devices and converter applications

Power electronics is undergoing significant changes both at the device and at the converter level. Wide bandgap power devices like SiC MOSFETs are increasingly implemented in automotive, grid and industrial drive applications with voltage ratings as high as 1.7kV now commercially available although much higher voltages have been demonstrated as research prototypes. In high power applications where high DC bus voltages are used, as is the case in voltage source converters for industrial drives, marine propulsion and grid connected energy conversion systems, it may be necessary to series connect power devices for OFF-state voltage sharing. In high power applications, before the advent of multi-level converters, series connection of IGBT power modules was commonplace especially for HVDC-voltage source converter applications. However, with the advent of the modular multi-level converter, where the AC voltage waveform is synthesized by discrete voltage steps, the need for series connected is obviated. Most HVDC-VSC applications are now implemented by modular-multi-level converters. However, in some applications like VSCs for distribution network power conversion, there can be a combination between series connection of power devices and multi-level converter. Traditionally, voltage balancing in series connected power devices was achieved using snubber capacitors for dynamic voltage sharing and resistors for static voltage sharing. However, the use of snubber capacitors reduces the switching speed of the converter thereby defeating the purpose of using SiC power devices especially in power converters with high switching frequencies. To avoid this, active gate driving techniques that avoid the use of snubber capacitors during switching are under intensive research focus. This involves intelligent gate drivers capable of dynamically adjusting the gate pulse during switching. To use these gate drivers, it is necessary to explore the boundaries of static and dynamic voltage imbalance in series connected power devices. For example, it is necessary to understand how differences in device junction temperature and gate driver switching rates affects voltage divergence between series connected devices and how this differs between silicon IGBTs and SiC MOSFETs. This is similarly the case between series connected silicon PiN diodes and SiC Schottky diodes. Since silicon IGBTs and PiN diodes respectively exhibit tails currents and reverse recovery during turn-OFF, the dynamics of voltage divergence between series devices will differ from unipolar SiC power devices. Furthermore, the leakage current mechanisms determine the OFF-state voltage balancing dynamics and since Si IGBTs have different leakage current mechanisms from SiC devices, OFF-state voltage balancing in series connected devices will be different between the technologies. The contribution of this thesis is using finite element and compact device models backed by experimental measurements to investigate static and dynamic voltage imbalance in series connected power devices. Starting from the fundamental physics behind device operation, this thesis explores how the leakage currents and tail currents affects voltage divergence in series silicon bipolar devices compared to SiC power devices. This analysis is compared with how the switching dynamics peculiar to fast switching SiC devices affects voltage balancing in series connected SiC devices. Simulations and measurements show that series connected SiC power devices are less prone of excessive voltage divergence due to the absence of tail currents compared to series connected silicon bipolar devices where voltage divergence due to tail currents is evident. Reduced leakage currents due to the wide bandgap in SiC also ensures that it is less prone to voltage divergence (compared to silicon bipolar devices) under static OFF-state conditions. This means the snubber resistances can be increased thereby reducing the OFF-state power dissipation in series connected SiC devices. In the analysis of voltage sharing of series connected devices during the static ON-state and OFF-state it was shown that the zero-temperature coefficient of the power devices determines the voltage sharing and loss distribution in the ON-state while the leakage current and switching synchronization is critical in the OFF-state. Simulations and measurements in this thesis show that the higher ZTC points in silicon bipolar devices compared to SiC unipolar devices means that ON-state voltage divergence depends on the load current. The dominant failure mode for series connected power devices is failure under dynamic avalanche which occurs in cases of extreme uncontrolled voltage divergence. In the investigations of the switching transient behaviour of series connected IGBT and SiC MOSFETs during turn-OFF, it was shown that the voltage imbalance for Si IGBT is highly dependent on the carrier concentration in the drift region during switching while for SiC MOSFET it depends on the switching time constant of the gate voltage and the rate that the MOS-channel cuts the current. The thesis also explores the limits of power device performance under dynamic avalanche conditions for both series silicon bipolar and SiC unipolar devices. In the analysis of SOA of series connected devices it was discussed that the SOA is reduced by increased switching rates and DC link voltages. Finally, the thesis explores the 3L-NPC converter and how the power factor of the load on the AC side of the converter alters the power dissipation sharing between the devices. The results show that loss distribution between the devices in the converter is not just affected by the load power factor but also by the switching frequency

Disseny microelectrnic de circuits discriminadors de polsos pel detector LHCb

The aim of this thesis is to present a solution for implementing the front end system of the Scintillator Pad Detector (SPD) of the calorimeter system of the LHCb experiment that will start in 2008 at the Large Hadron Collider (LHC) at CERN. The requirements of this specific system are discussed and an integrated solution is presented, both at system and circuit level. We also report some methodological achievements. In first place, a method to study the PSRR (and any transfer function) in fully differential circuits taking into account the effect of parameter mismatch is proposed. Concerning noise analysis, a method to study time variant circuits in the frequency domain is presented and justified. This would open the possibility to study the effect of 1/f noise in time variants circuits. In addition, it will be shown that the architecture developed for this system is a general solution for front ends in high luminosity experiments that must be operated with no dead time and must be robust against ballistic deficit