Design of dual-band matching network for highly efficient power amplifier

In the last decades wireless communications has been growing tremendously and given that the trend will most likely continue at a cumulative pace it is imperative that in the future, the transceivers designed need to operate at a near ideal energy efficiency on new frequency bands demanded by the 5G standard. Since transmitters are the corner stone of any wireless communication systems and that power amplifier (PA) is a high power consuming device within it. It is evident that the design of a highly efficient PA might tackle the significant portion of power loss within RF and microwave systems. The design of PA proposed in this work is aimed at dual band frequencies based on the LTE standards of LTE 42 and LTE 43 having range of 3.4 GHz to 3.6 GHz and 3.6 GHz to 3.8 GHz respectively. The design of a PA begins at characterizing the transistor employed then followed by conjugate matching of the input aimed at the gate. In the design for a highly efficient power amplifier, the design of the OMN plays a pivotal role. This is usually achieved by employing load pull techniques aimed at the drain to find the optimum impedance requirement at desired frequency. Then by employing band-pass filters aimed only to allow the two LTE bands to pass through will cause all the other harmonic frequencies suppression. Having an ideal efficiency of 100% and their simplistic design over other PA classes makes the Class E amplifier a viable choice. Although theoretically Class E amplifier have an ideal efficiency, we expect by achieving 60% to 80% efficiency will be an acceptable target since in practice the efficiency largely depends on the type of transistor being implemented in the PA system

Efficient and Wideband Load Modulated Power Amplifiers for Wireless Communication

The increasing demand for mobile data traffic has resulted in new challenges and requirements for the development of the wireless communication infrastructure. With the transition to higher frequencies and multi-antenna systems, radio frequency (RF) hardware performance, especially the power amplifier (PA), becomes increasingly important. Enhancing PA energy efficiency and bandwidth is vital for maximizing channel capacity, reducing operational costs, and facilitating integration.In the first part of the thesis, the bandwidth limitations of the standard two-way Doherty PA are discussed. A comprehensive analysis is provided, and the frequency responses of different Doherty combiner networks are presented. Furthermore, a Doherty combiner network is proposed, notable for its inherent broadband frequency and its capacity to account for the influence of output parasitics and packaged components from the active devices. The introduced Doherty combiner network is experimentally verified by a wideband gallium nitride (GaN) Doherty PA operating over 1.6-2.7 GHz.In the second part of the thesis, an analytically based combiner synthesis approach for the three-stage Doherty PA is proposed and presented. A compact output combiner network, together with the input phase delays, is derived directly from transistor load-pull data and the PA design requirements. The technique opens up new design space for three-stage Doherty PAs with reconfigurable high-efficiency power back-off levels. The utility of the proposed technique is demonstrated by the implementation of a 30-W GaN three-stage Doherty PA prototype at 2.14 GHz. Measurements show that a drain efficiency of 68% and 55% is exhibited at 6- and 10-dB back-off power, respectively.In the third part, a new PA architecture named the circulator load modulated amplifier (CLMA), is proposed. This architecture utilizes active load modulation for achieving enhanced back-off efficiency. Two active devices are incorporated in this innovative architecture, and a non-reciprocal circulator-based combiner is leveraged. Following this, the sequential CLMA (SCLMA) is introduced, characterized by its ability to enhance back-off efficiency without the necessity of load modulation. GaN demonstrator circuits for both CLMA and SCLMA architectures, whether with dual-input or RF single-input, are designed and fabricated, with excellent performance being measured.\ua0The thesis contributes novel design techniques and architectures to enhance PA efficiency and bandwidth. These findings pave the way for energy-efficient and adaptable RF transmitters in future wireless communication systems

Efficient and Linear CMOS Power Amplifier and Front-end Design for Broadband Fully-Integrated 28-GHz 5G Phased Arrays

Demand for data traffic on mobile networks is growing exponentially with time and on a global scale. The emerging fifth-generation (5G) wireless standard is being developed with millimeter-wave (mm-Wave) links as a key technological enabler to address this growth by a 2020 time frame. The wireless industry is currently racing to deploy mm-Wave mobile services, especially in the 28-GHz band. Previous widely-held perceptions of fundamental propagation limitations were overcome using phased arrays. Equally important for success of 5G is the development of low-power, broadband user equipment (UE) radios in commercial-grade technologies. This dissertation demonstrates design methodologies and circuit techniques to tackle the critical challenge of key phased array front-end circuits in low-cost complementary metal oxide semiconductor (CMOS) technology. Two power amplifier (PA) proof-of-concept prototypes are implemented in deeply scaled 28- nm and 40-nm CMOS processes, demonstrating state-of-the-art linearity and efficiency for extremely broadband communication signals. Subsequently, the 40 nm PA design is successfully embedded into a low-power fully-integrated transmit-receive front-end module. The 28 nm PA prototype in this dissertation is the first reported linear, bulk CMOS PA targeting low-power 5G mobile UE integrated phased array transceivers. An optimization methodology is presented to maximizing power added efficiency (PAE) in the PA output stage at a desired error vector magnitude (EVM) and range to address challenging 5G uplink requirements. Then, a source degeneration inductor in the optimized output stage is shown to further enable its embedding into a two-stage transformer-coupled PA. The inductor helps by broadening inter-stage impedance matching bandwidth, and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured Pout/PAE at −25 dBc EVM for a 250 MHz-wide, 64-QAM orthogonal frequency division multiplexing (OFDM) signal with 9.6 dB peak-to-average power ratio (PAPR). The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6dB back-off from saturation. To the best of the author’s knowledge, these are the highest measured PAE values among published K- and K a-band CMOS PAs to date. To drastically extend the communication bandwidth in 28 GHz-band UE devices, and to explore the potential of CMOS technology for more demanding access point (AP) devices, the second PA is demonstrated in a 40 nm process. This design supports a signal radio frequency bandwidth (RFBW) >3× the state-of-the-art without degrading output power (i.e. range), PAE (i.e. battery life), or EVM (i.e. amplifier fidelity). The three-stage PA uses higher-order, dual-resonance transformer matching networks with bandwidths optimized for wideband linearity. Digital gain control of 9 dB range is integrated for phased array operation. The gain control is a needed functionality, but it is largely absent from reported high-performance mm-Wave PAs in the literature. The PA is fabricated in a 1P6M 40 nm CMOS LP technology with 1.1 V supply, and achieves Pout/PAE of +6.7 dBm/11% for an 8×100 MHz carrier aggregation 64-QAM OFDM signal with 9.7 dB PAPR. This PA therefore is the first to demonstrate the viability of CMOS technology to address even the very challenging 5G AP/downlink signal bandwidth requirement. Finally, leveraging the developed PA design methodologies and circuits, a low power transmit-receive phased array front-end module is fully integrated in 40 nm technology. In transmit-mode, the front-end maintains the excellent performance of the 40 nm PA: achieving +5.5 dBm/9% for the same 8×100 MHz carrier aggregation signal above. In receive-mode, a 5.5 dB noise figure (NF) and a minimum third-order input intercept point (IIP₃) of −13 dBm are achieved. The performance of the implemented CMOS frontend is comparable to state-of-the-art publications and commercial products that were very recently developed in silicon germanium (SiGe) technologies for 5G communication

Vidutinių dažnių 5G belaidžių tinklų galios stiprintuvų tyrimas

This dissertation addresses the problems of ensuring efficient radio fre-quency transmission for 5G wireless networks. Taking into account, that the next generation 5G wireless network structure will be heterogeneous, the device density and their mobility will increase and massive MIMO connectivity capability will be widespread, the main investigated problem is formulated – increasing the efficiency of portable mid-band 5G wireless network CMOS power amplifier with impedance matching networks. The dissertation consists of four parts including the introduction, 3 chapters, conclusions, references and 3 annexes. The investigated problem, importance and purpose of the thesis, the ob-ject of the research methodology, as well as the scientific novelty are de-fined in the introduction. Practical significance of the obtained results, defended state-ments and the structure of the dissertation are also included. The first chapter presents an extensive literature analysis. Latest ad-vances in the structure of the modern wireless network and the importance of the power amplifier in the radio frequency transmission chain are de-scribed in detail. The latter is followed by different power amplifier archi-tectures, parameters and their improvement techniques. Reported imped-ance matching network design methods are also discussed. Chapter 1 is concluded distinguishing the possible research vectors and defining the problems raised in this dissertation. The second chapter is focused around improving the accuracy of de-signing lumped impedance matching network. The proposed methodology of estimating lumped inductor and capacitor parasitic parameters is dis-cussed in detail provi-ding complete mathematical expressions, including a summary and conclusions. The third chapter presents simulation results for the designed radio fre-quency power amplifiers. Two variations of Doherty power amplifier archi-tectures are presented in the second part, covering the full step-by-step de-sign and simulation process. The latter chapter is concluded by comparing simulation and measurement results for all designed radio frequency power amplifiers. General conclusions are followed by an extensive list of references and a list of 5 publications by the author on the topic of the dissertation. 5 papers, focusing on the subject of the discussed dissertation, have been published: three papers are included in the Clarivate Analytics Web of Sci-ence database with a citation index, one paper is included in Clarivate Ana-lytics Web of Science database Conference Proceedings, and one paper has been published in unreferred international conference preceedings. The au-thor has also made 9 presentations at 9 scientific conferences at a national and international level.Dissertatio

Design of a wideband doherty power amplifier with high efficiency for 5g application

This paper discusses the design of a wideband class AB-C Doherty power amplifier suitable for 5G applications. Theoretical analysis of the output matching network is presented, focusing on the impact of the non-ideally infinite output impedance of the auxiliary amplifier in back off, due to the device’s parasitic elements. By properly accounting for this effect, the designed output matching network was able to follow the desired impedance trajectories across the 2.8 GHz to 3.6 GHz range (fractional bandwidth = 25%), with a good trade-off between efficiency and bandwidth. The Doherty power amplifier was designed with two 10 W packaged GaN HEMTs. The measurement results showed that it provided 43 dBm to 44.2 dBm saturated output power and 8 dB to 13.5 dB linear power gain over the entire band. The achieved drain efficiency was between 62% and 76.5% at saturation and between 44% and 56% at 6 dB of output power back-off

A review of technologies and design techniques of millimeter-wave power amplifiers

his article reviews the state-of-the-art millimeter-wave (mm-wave) power amplifiers (PAs), focusing on broadband design techniques. An overview of the main solid-state technologies is provided, including Si, gallium arsenide (GaAs), GaN, and other III-V materials, and both field-effect and bipolar transistors. The most popular broadband design techniques are introduced, before critically comparing through the most relevant design examples found in the scientific literature. Given the wide breadth of applications that are foreseen to exploit the mm-wave spectrum, this contribution will represent a valuable guide for designers who need a single reference before adventuring in the challenging task of the mm-wave PA design

Wideband Watt-Level Spatial Power-Combined Power Amplifier in SiGe BiCMOS Technology for Efficient mm-Wave Array Transmitters

The continued demand for high-speed wireless communications is driving the development of integrated high-power transmitters at millimeter wave (mm-Wave) frequencies. Si-based technologies allow achieving a high level of integration but usually provide insufficient generated RF power to compensate for the increased propagation and material losses at mm-Wave bands due to the relatively low breakdown voltage of their devices. This problem can be reduced significantly if one could combine the power of multiple active devices on each antenna element. However, conventional on-chip power combining networks have inherently high insertion losses reducing transmitter efficiency and limiting its maximum achievable output power.This work presents a non-conventional design approach for mm-Wave Si-based Watt-level power amplifiers that is based on novel power-combining architecture, where an array of parallel custom PA-cells suited on the same chip is interfaced to a single substrate integrated waveguide (to be a part of an antenna element). This allows one to directly excite TEm0 waveguide modes with high power through spatial power combining functionality, obviating the need for intermediate and potentially lossy on-chip power combiners. The proposed solution offers wide impedance bandwidth (50%) and low insertion losses (0.4 dB), which are virtually independent from the number of interfaced PA-cells. The work evaluates the scalability bounds of the architecture as well as discusses the critical effects of coupled non-identical PA-cells, which are efficiently reduced by employing on-chip isolation load resistors.The proposed architecture has been demonstrated through an example of the combined PA with four differential cascode PA-cells suited on the same chip, which is flip-chip interconnected to the combiner placed on a laminate. This design is implemented in a 0.25 um SiGe BiCMOS technology. The PA-cell has a wideband performance (38.6%) with both high peak efficiency (30%) and high saturated output power (24.9 dBm), which is the highest reported output power level obtained without the use of circuit-level power combining in Si-based technologies at Ka-band. In order to achieve the optimal system-level performance of the combined PA, an EM-circuit-thermal optimization flow has been proposed, which accounts for various multiphysics effects occurring in the joint structure. The final PA achieves the peak PAE of 26.7% in combination with 30.8 dBm maximum saturated output power, which is the highest achievable output power in practical applications, where the 50-Ohms load is placed on a laminate. The high efficiency (>20%) and output power (>29.8 dBm) over a wide frequency range (30%) exceed the state-of-the-art in Si-based PAs

Millimeter-Wave Active Array Antennas Integrating Power Amplifier MMICs through Contactless Interconnects

Next-generation mobile wireless technologies demand higher data capacity than the modern sub-6 GHz technologies can provide. With abundantly available bandwidth, millimeter waves (e.g., Ka/K bands) can offer data rates of around 10 Gbit/s; however, this shift to higher frequency bands also leads to at least 20 dB more free-space path loss. Active integrated antennas have drawn much attention to compensate for this increased power loss with high-power, energy- efficient, highly integrated array transmitters. Traditionally, amplifiers and antennas are designed separately and interconnected with 50 Ohm intermediate impedance matching networks. The design process typically de-emphasizes the correlation between antenna mutual coupling effects and amplifier nonlinearity, rendering high power consumption and poor linearity. This research aims to overcome the technical challenges of millimeter-wave active integrated array antennas on delivering high power (15–25 dBm) and high energy efficiency (≥25%) with above 10% bandwidth. A co-design methodology was proposed to maximize the output power, power efficiency, bandwidth, and linearity with defined optimal interface impedances. Contrary to conventional approaches, this methodology accounts for the correlation between mutual coupling effects and nonlinearity. A metallic cavity-backed bowtie slot antenna, with sufficient degrees of freedom in synthesizing a non 50 Ohm complex-valued optimal impedance, was adopted for high radiation efficiency and enhanced bandwidth. To overcome interconnection’s bandwidth and power loss limitations, an on-chip E-plane probe contactless transition be- tween the antenna and amplifier was proposed. An array of such antennas be- comes connected bowtie slots, allowing for wideband and wide-scan array performance. An infinite array active integrated unit cell approach was introduced for large-scale (aperture area ≈100 λ2) active array designs. The proposed co-design flow is applied in designing a Ka-band wideband, wide scan angle (\ub155\ub0/\ub140\ub0) active array antenna, consisting of the connected bowtie slot radiator fed through the on-chip probe integrated onto the output of a class AB GaAs pHEMT MMIC PA. The infinite array performance of such elements is experimentally verified, presenting a 11.3% bandwidth with a peak 40% power efficiency, 28 dBm EIRP, and 22 dBm saturated power