A Millimeter-Wave Coexistent RFIC Receiver Architecture in 0.18-µm SiGe BiCMOS for Radar and Communication Systems

Innovative circuit architectures and techniques to enhance the performance of several key BiCMOS RFIC building blocks applied in radar and wireless communication systems operating at the millimeter-wave frequencies are addressed in this dissertation. The former encapsulates the development of an advanced, low-cost and miniature millimeter-wave coexistent current mode direct conversion receiver for short-range, high-resolution radar and high data rate communication systems. A new class of broadband low power consumption active balun-LNA consisting of two common emitters amplifiers mutually coupled thru an AC stacked transformer for power saving and gain boosting. The active balun-LNA exhibits new high linearity technique using a constant gm cell transconductance independent of input-outputs variations based on equal emitters’ area ratios. A novel multi-stages active balun-LNA with innovative technique to mitigate amplitude and phase imbalances is proposed. The new multi-stages balun-LNA technique consists of distributed feed-forward averaging recycles correction for amplitude and phase errors and is insensitive to unequal paths parasitic from input to outputs. The distributed averaging recycles correction technique resolves the amplitude and phase errors residuals in a multi-iterative process. The new multi-stages balun-LNA averaging correction technique is frequency independent and can perform amplitude and phase calibrations without relying on passive lumped elements for compensation. The multi-stage balun-LNA exhibits excellent performance from 10 to 50 GHz with amplitude and phase mismatches less than 0.7 dB and 2.86º, respectively. Furthermore, the new multi-stages balun-LNA operates in current mode and shows high linearity with low power consumption. The unique balun-LNA design can operates well into mm-wave regions and is an integral block of the mm-wave radar and communication systems. The integration of several RFIC blocks constitutes the broadband millimeter-wave coexistent current mode direct conversion receiver architecture operating from 22- 44 GHz. The system and architectural level analysis provide a unique understanding into the receiver characteristics and design trade-offs. The RF front-end is based on the broadband multi-stages active balun-LNA coupled into a fully balanced passive mixer with an all-pass in-phase/quadrature phase generator. The trans-impedance amplifier converts the input signal current into a voltage gain at the outputs. Simultaneously, the high power input signal current is channelized into an anti-aliasing filter with 20 dB rejection for out of band interferers. In addition, the dissertation demonstrates a wide dynamic range system with small die area, cost effective and very low power consumption

A Millimeter-Wave Coexistent RFIC Receiver Architecture in 0.18-µm SiGe BiCMOS for Radar and Communication Systems

Innovative circuit architectures and techniques to enhance the performance of several key BiCMOS RFIC building blocks applied in radar and wireless communication systems operating at the millimeter-wave frequencies are addressed in this dissertation. The former encapsulates the development of an advanced, low-cost and miniature millimeter-wave coexistent current mode direct conversion receiver for short-range, high-resolution radar and high data rate communication systems. A new class of broadband low power consumption active balun-LNA consisting of two common emitters amplifiers mutually coupled thru an AC stacked transformer for power saving and gain boosting. The active balun-LNA exhibits new high linearity technique using a constant gm cell transconductance independent of input-outputs variations based on equal emitters’ area ratios. A novel multi-stages active balun-LNA with innovative technique to mitigate amplitude and phase imbalances is proposed. The new multi-stages balun-LNA technique consists of distributed feed-forward averaging recycles correction for amplitude and phase errors and is insensitive to unequal paths parasitic from input to outputs. The distributed averaging recycles correction technique resolves the amplitude and phase errors residuals in a multi-iterative process. The new multi-stages balun-LNA averaging correction technique is frequency independent and can perform amplitude and phase calibrations without relying on passive lumped elements for compensation. The multi-stage balun-LNA exhibits excellent performance from 10 to 50 GHz with amplitude and phase mismatches less than 0.7 dB and 2.86º, respectively. Furthermore, the new multi-stages balun-LNA operates in current mode and shows high linearity with low power consumption. The unique balun-LNA design can operates well into mm-wave regions and is an integral block of the mm-wave radar and communication systems. The integration of several RFIC blocks constitutes the broadband millimeter-wave coexistent current mode direct conversion receiver architecture operating from 22- 44 GHz. The system and architectural level analysis provide a unique understanding into the receiver characteristics and design trade-offs. The RF front-end is based on the broadband multi-stages active balun-LNA coupled into a fully balanced passive mixer with an all-pass in-phase/quadrature phase generator. The trans-impedance amplifier converts the input signal current into a voltage gain at the outputs. Simultaneously, the high power input signal current is channelized into an anti-aliasing filter with 20 dB rejection for out of band interferers. In addition, the dissertation demonstrates a wide dynamic range system with small die area, cost effective and very low power consumption

IC-Antenna Co-Integration for Efficient and Scalable Millimeter-Wave Antenna Interfaces

Millimeter-wave (mm-wave) technology promises high speed, high system capacity and low latency interconnects with reduced cost. Applications like high data-rate wireless links, next generation automotive sensors and security body scanners highly depend on mm-wave technology innovations. As operating frequency moves to higher mm-wave bands, shrinking antenna dimensions enable co-integration of IC and antenna. Limited transistor output power at mm-wave requires multi-element arrays to satisfy communication and radar link budgets. This dissertation presents a wafer-scale compatible IC-antenna co-integration for efficient and scalable mm-wave antenna interfaces. The proposed IC-antenna co-integration approach is demonstrated through single antenna transmitters, a concurrent dual-polarization receiver front-end and polarization-duplex transmitter/receiver front-end. Chapter 2 discusses the challenge of mm-wave IC-antenna interfaces with prior art including antenna-in-package (AiP) and on-chip antennas. The 60 GHz efficient, scalable and wafer-scale compatible IC-antenna co-integration approach is presented demonstrating wide bandwidth and large efficiency which are comparable to system-level AiP techniques at a lower cost and fabrication complexity. Chapter 3 extends the proposed approach to a concurrent 60 GHz dual-polarization receiver front-end for short-range imaging/communication applications and polarization diversity based MIMO links. Active cancellation between orthogonal polarizations is adopted to achieve ∼ 30 dB cross-polarization leakage cancellation and concurrent dual-pol reception. Chapter 4 presents a 60 GHz simultaneous transmit and receive front-end to achieve efficient polarization-duplex operation based on dual-polarization IC-antenna co-integration. Transmitter leakage is suppressed at receiver input and output by intrinsic antenna isolation and a feed-forward passive canceller. Total average self-interference cancellation >40 dB is achieved for 1.07 GHz RF bandwidth at 60 GHz in the presence of a reflector

High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works

High performance building blocks for wireless receiver: multi-stage amplifiers and low noise amplifiers

Different wireless communication systems utilizing different standards and for multiple applications have penetrated the normal people's life, such as Cell phone, Wireless LAN, Bluetooth, Ultra wideband (UWB) and WiMAX systems. The wireless receiver normally serves as the primary part of the system, which heavily influences the system performance. This research concentrates on the designs of several important blocks of the receiver; multi-stage amplifier and low noise amplifier. Two novel multi-stage amplifier typologies are proposed to improve the bandwidth and reduce the silicon area for the application where a large capacitive load exists. They were designed using AMI 0.5 m µ CMOS technology. The simulation and measurement results show they have the best Figure-of-Merits (FOMs) in terms of small signal and large signal performances, with 4.6MHz and 9MHz bandwidth while consuming 0.38mW and 0.4mW power from a 2V power supply. Two Low Noise Amplifiers (LNAs) are proposed, with one designed for narrowband application and the other for UWB application. A noise reduction technique is proposed for the differential cascode Common Source LNA (CS-LNA), which reduces the LNA Noise Figure (NF), increases the LNA gain, and improves the LNA linearity. At the same time, a novel Common Gate LNA (CG-LNA) is proposed for UWB application, which has better linearity, lower power consumption, and reasonable noise performance. Finally a novel practical current injection built-in-test (BIT) technique is proposed for the RF Front-end circuits. If the off-chip component Lg and Rs values are well controlled, the proposed technique can estimate the voltage gain of the LNA with less than 1dB (8%) error

Design of a 3.1-4.8 GHZ RF front-end for an ultra wideband receiver

IEEE 802.15 High Rate Alternative PHY task group (TG3a) is working to define a protocol for Wireless Personal Area Networks (WPANs) which makes it possible to attain data rates of greater than 110Mbps. Ultra Wideband (UWB) technology utilizing frequency band of 3.168 GHz 10.6 GHz is an emerging solution to this with data rates of 110, 200 and 480 Mbps. Initially, UWB mode I devices using only 3.168 GHz 4.752 GHz have been proposed. Low Noise Amplifier (LNA) and I-Q mixers are key components constituting the RF front-end. Performance of these blocks is very critical to the overall performance of the receiver. In general, main considerations for the LNA are low noise, 50 broadband input matching, high gain with maximum flatness and good linearity. For the mixers, it is essential to attain low flicker noise performance coupled with good conversion gain. Proposed LNA architecture is a derivative of inductive source degenerated topology. Broadband matching at the LNA output is achieved using LC band-pass filter. To obtain high gain with maximum flatness, an LC band-pass filter is used at its output. Proposed LNA achieved a gain of 15dB, noise figure of less than 2.6dB and IIP3 of more than -7dBm. Mixer is a modified version of double balanced Gilbert cell topology where both I and Q channel mixers are merged together. Frequency response of each sub-band is matched by using an additional inductor, which further improves the noise figure and conversion gain. Current bleeding scheme is used to further reduce the low frequency noise. Mixer achieves average conversion gain of 14.5dB, IIP3 more than 6dBm and Double Side Band (DSB) noise figure less than 9dB. Maximum variation in conversion gain is desired to be less than 1dB. Both LNA and mixers are designed to be fabricated in TSMC 0.18µm CMOS technology

High Performance Local Oscillator Design for Next Generation Wireless Communication

Local Oscillator (LO) is an essential building block in modern wireless radios. In modern wireless radios, LO often serves as a reference of the carrier signal to modulate or demod- ulate the outgoing or incoming data. The LO signal should be a clean and stable source, such that the frequency or timing information of the carrier reference can be well-defined. However, as radio architecture evolves, the importance of LO path design has become much more important than before. Of late, many radio architecture innovations have exploited sophisticated LO generation schemes to meet the ever-increasing demands of wireless radio performances. The focus of this thesis is to address challenges in the LO path design for next-generation high performance wireless radios. These challenges include (1) Congested spectrum at low radio frequency (RF) below 5GHz (2) Continuing miniaturization of integrated wireless radio, and (3) Fiber-fast (>10Gb/s) mm-wave wireless communication. The thesis begins with a brief introduction of the aforementioned challenges followed by a discussion of the opportunities projected to overcome these challenges. To address the challenge of congested spectrum at frequency below 5GHz, novel ra- dio architectures such as cognitive radio, software-defined radio, and full-duplex radio have drawn significant research interest. Cognitive radio is a radio architecture that opportunisti- cally utilize the unused spectrum in an environment to maximize spectrum usage efficiency. Energy-efficient spectrum sensing is the key to implementing cognitive radio. To enable energy-efficient spectrum sensing, a fast-hopping frequency synthesizer is an essential build- ing block to swiftly sweep the carrier frequency of the radio across the available spectrum. Chapter 2 of this thesis further highlights the challenges and trade-offs of the current LO gen- eration scheme for possible use in sweeping LO-based spectrum analysis. It follows by intro- duction of the proposed fast-hopping LO architecture, its implementation and measurement results of the validated prototype. Chapter 3 proposes an embedded phase-shifting LO-path design for wideband RF self-interference cancellation for full-duplex radio. It demonstrates a synergistic design between the LO path and signal to perform self-interference cancellation. To address the challenge of continuing miniaturization of integrated wireless radio, ring oscillator-based frequency synthesizer is an attractive candidate due to its compactness. Chapter 4 discussed the difficulty associated with implementing a Phase-Locked Loop (PLL) with ultra-small form-factor. It further proposes the concept sub-sampling PLL with time- based loop filter to address these challenges. A 65nm CMOS prototype and its measurement result are presented for validation of the concept. In shifting from RF to mm-wave frequencies, the performance of wireless communication links is boosted by significant bandwidth and data-rate expansion. However, the demand for data-rate improvement is out-pacing the innovation of radio architectures. A >10Gb/s mm-wave wireless communication at 60GHz is required by emerging applications such as virtual-reality (VR) headsets, inter-rack data transmission at data center, and Ultra-High- Definition (UHD) TV home entertainment systems. Channel-bonding is considered to be a promising technique for achieving >10Gb/s wireless communication at 60GHz. Chapter 5 discusses the fundamental radio implementation challenges associated with channel-bonding for 60GHz wireless communication and the pros and cons of prior arts that attempted to address these challenges. It is followed by a discussion of the proposed 60GHz channel- bonding receiver, which utilizes only a single PLL and enables both contiguous and non- contiguous channel-bonding schemes. Finally, Chapter 6 presents the conclusion of this thesis

CMOS RF front-end design for terrestrial and mobile digital television systems

With the increasing demand for high quality TV service, digital television (DTV) is replacing the conventional analog television. DTV tuner is one of the most critical blocks of the DTV receiver system; it down-converts the desired DTV RF channel to baseband or a low intermediate frequency with enough quality. This research is mainly focused on the analysis and realization of low-cost low-power front-ends for ATSC terrestrial DTV and DVB-H mobile DTV tuner systems. For the design of the ATSC terrestrial tuner, a novel double quadrature tuner architecture, which can not only minimize the tuner power consumption but also achieve the fully integration, has been proposed. A double quadrature down-converter has been designed and fabricated with TSMC 0.35õm CMOS technology; the measurement results verified the proposed concepts. For the mobile DTV tuner, a zero-IF architecture is used and it can achieve the DVB-H specifications with less than 200mW power consumption. In the implementation of the mobile DVB-H tuner, a novel RF variable gain amplifier (RFVGA) and a low flicker noise current-mode passive mixer have been proposed. The proposed RFVGA achieves high dynamic range and robust input impedance matching performance, which is the main design challenge for the traditional implementations. The current-mode passive mixer achieves high-gain, low noise (especially low flicker noise) and high-linearity (over 10dBm IIP3) with low power supplies; it is believed that this is a promising topology for low voltage high dynamic range mixer applications. The RFVGA has been fabricated in TSMC 0.18õm CMOS technology and the measurement results agree well with the theoretical ones

Bandwidth Enhancement Techniques For Cmos Transimpedance Amplifier

Tez (Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2016Thesis (PhD) -- İstanbul Technical University, Institute of Science and Technology, 2016CMOS Transferempedans Kuvvetlendiricinin bandgenis¸lig˘ i bas¸arımını gelis¸tirmeye yönelik teknikler haberles¸me teknolojisinde ve uygulamalarında ortaya çıkan hızlı gelis¸meler ve uygulamalar verilere hızlı eris¸im avantajı yanında hızlı hesaplama ve haberles¸me tekniklerine imkan veren bir bilgi çag˘ ını ortaya çıkarmıs¸tır. Sürekli artan hızlı bilgi transferi ihtiyacı, hızlı elemanların ve tümdevrelerin tasarımına yönelik aras¸tırmalara liderlik eden optik haberles¸me teknig˘ ini dog˘ urmus¸tur. Veri iletimi için mevcut ortamlar arasında optik fiber yapıları en iyi bas¸arımı sunmaktadır. Günümüzde optik fiberler çok yog˘ un sayısal veri transferinde genis¸ kullanım alanı bulmaktadır. Yog˘ un veri aktarımı kilometrelerce uzunlukta optik fiberler üzerinde önemli bir kayıp olmaksızın yapılabilmektedir. Normal s¸artlarda, is¸aret aktarımının ıs¸ık ile yapılması durumunda ortaya çıkan kayıp elektriksel yolla yapılan aktarıma gore daha düs¸üktür. Optik fiberler genel bas¸arımı iyiles¸tirmenin yanında düs¸ük maliyet avantajını da sunmaktadır. En yüksek teknolojilerde, optik fiber elemanları ve sistemleri çok yog˘ un veri aktarımı amacıyla kullanılmaktadır. Sonuç olarak optik fiber teknolojisi düs¸ük kayıpla çok yog˘ un veri aktarımını az maliyetle sunabilen bir teknoloji olarak günümüzde çok önemli bir konuma sahiptir. Genel olarak, optik haberles¸me sistemlerinde kullanılan analog devreler Galyum Arsenik (GaAs) veya Indiyum Fosfid (InP) teknolojileri ile üretilmektedir. Bu prosesler yüksek hızlı devreler için olus¸turulmakta olup optik haberles¸me sistemlerinin ihtiyaç duydug˘ u yüksek band genis¸lig˘ ine sahip devreleri üretmek için genellikle tek alternatif olarak kars¸ımıza çıkmaktadırlar. Bununla birlikte, CMOS proseslerinde ortaya çıkan hızlı gelis¸meler sayesinde daha yüksek bas¸arımlara sahip analog devreleri CMOS proses kullanarak tasarlama ve gerçekles¸tirme imkanları gittikçe artmaktadır. CMOS prosesin tercih edilmesine sebep olan en önemli avantaj maliyetlerde ortaya çıkan büyük düs¸üs¸tür. CMOS proseslerin maliyetinin düs¸ük olmasının sebebi, büyük alan kullanımı gerektiren sayısal devre gerçekles¸tirmelerinde çok genis¸ bir kullanıma sahip olmasıdır. CMOS prosesin dig˘ er bir avantajı sayısal ve analog devrelerin aynı taban üzerinde gerçekles¸tirilmesine imkan vermesidir. Transferempedans kuvvetlendirici (TIA) optik haberles¸me alıcılarındaki ilk blok olup giris¸indeki akımı çıkıs¸ında gerilime dönüs¸türmektedir. Tipik bir TIA’nın önemli bas¸arım ihtiyaçları genis¸ bandgenis¸lig˘ i, yüksek transferempedans kazancı, düs¸ük gürültü, düs¸ük güç tüketimi ve küçük grup geçikme deg˘ is¸im aralıg˘ ıdır. Nano teknolojilerdeki güncel gelis¸meler, optik alıcıların giris¸ katı uygulamalarında gerekli kolay bir s¸ekilde elde edilemeyen bas¸arımları sag˘ layabilen CMOS Transfer- empedans Kuvvetlendiricinin (TIA) tasarımını ekonomik hale getirmis¸tir. TIA tasarımında dikkat edilmesi gereken iki önemli mesele bandgenis¸lig˘ i ve giris¸ hassasiyetidir. TIA’nın bandgenis¸lig˘ i genellikle giris¸teki parasitic kapasite tarafından sınırlanmaktadır. TIA’nın bandgenis¸lig˘ i fotodiyot kapasitesi, transistor giris¸ kapasitesi ve transistor giris¸ direncinin belirledig˘ i RC zaman sabiti ile bulunabilir. Giris¸ hassasiyeti ise TIA’nın giris¸ gürültü akımından etkilenmektedir. Bundan dolayı TIA’nın bandgenis¸lig˘ i ve giris¸ is¸areti hassasiyeti bas¸arımlarını optimum bir s¸ekilde temin eden uygun devre topolojisinin belirlenmesi önemli bir meseledir. Bu tez, CMOS teknolojisi kullanan Transferempedans Kuvvetlendiricinin band- genis¸lig˘ i bas¸arımını gelis¸tirmeye yönelik yeni teknikler sunan bir çalıs¸madır. CMOS TIA’nın bandgenis¸lig˘ i bas¸arımını iyiles¸tirmeye yönelik farklı yaklas¸ımlar tez içerisinde gösterilmektedir. Bundan bas¸ka, bu çalıs¸ma transferempedansı kuvvetlendiricinin analizini ve tasarımını tam olarak anlamak için gerekli altyapı bilgisini de sunmaktadır. Bu tezde, sistemle devre tasarımı arasındaki bos¸lug˘ u doldurmak için s¸unlar yapılmıs¸tır: - Band genis¸lig˘ i bas¸arımının arttırılmasının matematiksel analizlerle anlas¸ılması. - Gerçekles¸tirilebilir yeni devre yapılarının tanıtılması. - Teklif edilen tasarımların CMOS teknolojisiyle gerçekles¸tirilebilirlig˘ inin kapsamlı ve detaylı simülasyonlar kullanılarak gösterilmesi. Sunulan yeni devre yapılarının ilki olarak, negatif empedans devresinin bandgenis¸lig˘ i artıs¸ı için kullanılabileceg˘ i bu tezde gösterilmis¸ olup bu teknik bu tezde TIA’nın çıkıs¸ kutpu için uygulanmaktadır. Bandgenis¸lig˘ i, kazancı (gmRout) arttırarak ve çıkıs¸ta aynı zaman sabiti korunarak arttırılabilir. Çıkıs¸ direnci arttırılarak kazanç (A) yükseltilebilir. Çıkıs¸ direnci çıkıs¸a uygulanacak bir negative direnç devresi ile arttırılabilir. Çıkıs¸ta aynı zaman sabitini korumak için ise negatif kapasite devresi kullanılabilir. Daha yüksek kazanç deg˘ eri (A) rezistif geribesleme sayesinde giris¸ direncini azaltarak giris¸ kutbunun yükselmesini sag˘ lamaktadır. Sonuç olarak, bandgenis¸lig˘ i bas¸arımında bir iyiles¸tirme elde edilebilmektedir. Teklif edilen topoloji ile 7GHz bandgenis¸lig˘ ine ve 54.3dB’lik kazanca sahip bir TIA tasarlanmıs¸tır. Teklif edilen TIA’nın 1.8V’luk besleme kaynag˘ ından çektig˘ i toplam güç 29mW’tır. Teklif edilen TIA’nın 0.18um CMOS proses ile post-serimi yapılmıs¸tır. Benzetimle elde edilmis¸ giris¸ gürültü akım yog˘ unlug˘ u 5.9pA/ Hz olup kapladıg˘ ı alan 230umX45um olmus¸tur. Tezde bir sonraki çalıs¸mada es¸les¸tirme teknig˘ i kullanılarak genis¸ bantlı bs¸r TIA tasarlanmıs¸tır. Giris¸te seri empedans es¸les¸tirme teknig˘ i ve çıkıs¸ta T tipi es¸les¸tirme yapısı birlikte kullanılarak TIA’nın bandgenis¸lig˘ i bas¸arımının iyi bir düzeyde iyiles¸tirilebileceg˘ i gösterilmis¸tir. Bu yaklas¸ım 0.18um CMOS teknolojisi ile yapılmıs¸ bir tasarım örneg˘ i ile desteklenmis¸tir. Post serim sonuçları 50fF’lık bir fotodiyot kapasitesi için 20GHz’lik bandgenis¸lig˘ i, 52.6dB’lik transferdirenci kazancı, 8.7pA/ Hz ‘lik giris¸ gürültü akımı ve 3pS’den daha az grup geçikmesi bas¸arımılarını vermis¸tir. Bu TIA uygulaması 1.8V’luk besleme kaynag˘ ından 1.3mW güç çekmis¸tir. Tezin üçüncü as¸amasında TIA band genis¸lig˘ i bas¸arımını arttırmaya yönelik bas¸ka bir yapı sunulmaktadır. Bu yapı, literatürde bilinen regule edilmis¸ ortak geçitli mimari ile birlikte farklı rezonans frekanslarına sahip iki rezonans devresinin paralel kullanımını içermektedir. Teklif edilen TIA devresinde, kapasite dejenarasyon ve seri endüktif tepe teknikleri kutup-sıfır kompanzasyonu için kullanılmıs¸tır. 100fF’lık fotodiyot kapasitesine sahip bir TIA 0.18um CMOS prosesi ili tasarlanmıs¸tır. Post-serim sonuçları 13GHz’lik bandgenis¸lig˘ i, 53dB’lik transferdirenci kazancı, 24pA/ Hz ‘lik xxvi giris¸ gürültü akımı ve 5pS’den daha az grup geçikmesi bas¸arımılarını vermis¸tir. Bu TIA uygulaması 1.8V’luk besleme kaynag˘ ından 11mW güç çekmis¸tir. Tezin dördüncü as¸amasında, regule edilmis¸ ortak geçitli mimari kullanan TIA’nın bandgenis¸lig˘ i bas¸arımını arttırmaya yönelik bir teknik tanıtılmıs¸tır. Bu teknik, resistif kompanzasyon teknig˘ ini ve merdiven es¸les¸tirme yapısını bir kaskod akım kaynag˘ ı ile birlikte kullanmaya dayanmaktadır. Bu yapının bas¸arımını göstermek amacıyla, 0.18um CMOS prosesi ile bir tasarım yapılmıs¸tır. Post-serim sonuçları 8.4GHz’lik bandgenis¸lig˘ i, 51.3dB’lik transferdirenci kazancı, 20pA/ Hz ‘lik giris¸ gürültü akımı ve 4pS’den daha az grup geçikmesi bas¸arımılarını vermis¸tir. Bu TIA uygulaması 1.8V’luk besleme kaynag˘ ından 17.8mW güç çekmis¸tir. Tezin son as¸amasında, tezde sunulan teknikler ve yapıların kendi aralarında kars¸ılas¸tırılması verilmektedir. Kars¸ılas¸tırma öncelikli olarak band genis¸lig˘ i, transferempedansı kazancı, gürültü, güç tüketimi, grup geçikme deg˘ is¸im aralıg˘ ı ve kapladıg˘ ı alan için yapılmaktadır. Bunlara ek olarak, sunulan yapıların kullandıg˘ ı tekniklerin avantajlı yanları ile birlikte (kararlılık üzerinde olus¸abilecek negatif etkiler gibi) dezavantajlı tarafları da tezin son as¸amasında verilmektedir. Tezin son as¸amasında yapılan kars¸ılas¸tırmalar, en iyi bant genis¸lig˘ i bas¸arımının es¸les¸tirme teknig˘ ini kullanan yapıdan elde edildig˘ ini göstermektedir. Bununla birlikte dig˘ er yapıların da band genis¸lig˘ i bas¸arımı üzerinde önemli iyiles¸tirmeler yaptıg˘ ı ortaya konulmaktadır. Gürültü açısından ise en yüksek bas¸arımın negatif empedans teknig˘ ini kullanan yapıda elde edildig˘ i görülmektedir. Bu yapı aynı zamanda düs¸ük alan kullanımı imkanı da sunmaktadır. Tezde sunulan dig˘ er iki yapı ise özellikle yüksek deg˘ erli fotodiyot kapasiteleri için incelenmis¸ olup band genis¸lig˘ i bas¸arımı üzerinde önemli iyiles¸tirmeler yaptıkları gösterilmektedir. Sonuç olarak, bu tezde transferempedans kuvvetlendiricinin bandgenis¸lig˘ i bas¸arımını iyiles¸tiren farklı teknikler sunulmakta olup bu teknikler ayrıntılı ve kars¸ılas¸tırmalı olarak incelenmektedir. Tezde verilen sonuçlar sunulan yeni tekniklerin bas¸arımlarının yüksek oldug˘ unu ve literature yeni ve güçlü alternatfiler sunuldug˘ unu göstermektedir. Tezde sunulan yaklas¸ımların ve tekniklerin gelecekte yapılacak benzer aras¸tırmalara hem yardımcı olacak hem de referans olacak nitelikte oldug˘ u düs¸ünülmektedir.The accelerated development of integrated systems in the communication technology and their application are among the significant technologies that have developed the information era by empowering high-speed computation and communication technique besides high-speed access to stored data. The continuous growth demand for high-speed transport of information has rekindled optical communications, leading to derived research on high-speed device and integrated circuit design. Among the available medium to transfer the data, optical fibers have the best performance. Optical fibers are very common these days to transport very high rate digital data. Such high speed data rates can be transported over kilometers of optical fiber and without significant loss. Normally loss is very low when the signal is transmitted using light rather than electrical signal. These fibers also have the advantage of being low cost in addition to improvement of performance. In state-of-the-art technology, fiber optic devices and systems are evidently employed to realize very high data rates. Fiber optic communication is a solution because high data rates can be transmitted through this high capacity cable with high performance. Traditionally, analog circuits used in optical communication systems are implemented using Gallium Arsenide (GaAs) or Indium Phosphide (InP) technologies. These processes are designed for high speed circuits, and have been traditionally the only technologies able to produce the high bandwidth circuits required in optical communication systems. However, due to the aggressive scaling of the CMOS process, it is now becoming possible to design high performance analog circuits in CMOS. The primary advantage of moving to a CMOS process is a dramatic reduction in cost due to its widespread use in high volume digital circuits. Another advantage of using CMOS is its ability to integrate digital and analog circuits onto the same substrate. Transimpedance amplifier (TIAs) is the first building block in the optical communication receiver that converts the small signal current to a corresponding output voltage signal. The important requirements of a typical TIA are large bandwidth, high transimpedance gain, low noise, low power consumption, and small group delay variation. Current developments in nanoscale technologies made it economically feasible to design CMOS transimpedance amplifier (TIA) that satisfies the stringent performances necessary for the front-end optical transceivers applications such as low power, low cost and high integration which offers the most economical solution in the consumer application market. In designing of TIA, the two major factors that must be considered are the bandwidth and the input sensitivity. The bandwidth of TIA is usually limited by the parasitic capacitance at the input stage, and it can be calculated by its RC time constant contributed by photodiode capacitance, parasitic capacitance and input resistance of the amplifier. The sensitivity is affected by the input current noise of the TIA. Therefore it is challenge to choose the suitable circuit topology that provides an optimal trade-off between bandwidth and input signal sensitivity for TIA. This thesis is an attempt toward providing novel techniques to extend the bandwidth of the transimpedance amplifier using CMOS technology. Different approaches used to improve the bandwidth of CMOS TIAs are covered. Moreover, this research provides the necessary background knowledge to fully understand the analysis and design of the transimpedance amplifier (TIA). Bridging the gap between system and circuit design is done by: Understanding the bandwidth expansion by mathematical analysis. Introducing new circuit architectures that can be realized. Demonstrating implementation of the proposed designs using extensive simulations in CMOS technology. It is shown in this thesis that, using a negative impedance NI circuit can be used for bandwidth extension. In our application, the negative impedance is incorporated into the output pole of TIA. The bandwidth can be improved by increasing the gain (A = gmRout ) and by maintaining the same time constant at the output pole. A better gain A can be obtained if the output resistance Rout is increased. Increasing Rout can be done by placing a negative resistance RIN in parallel with the output resistance Rout . In order to maintain the same time constant at the output node, a negative capacitance can be used. It have been reported that, the shunt feedback architecture is used to improve the bandwidth of TIA. Increasing the gain A effectively decreases the input resistance and hence increase the frequency of the input pole due to feedback. As a result, an improvement of the bandwidth can be obtained. Using the proposed topology, a wide band transimpedance amplifier with a bandwidth of 7 GH z and transimpedance gain of 54.3 dBΩ is achieved. The total power consumption of the proposed TIA from the 1.8 V power supply is 29 mW . The TIA is designed in 0.18 µ m CMOS technology. The simulated input referred noise current spectral density is 5.9 pA/√H z and the TIA occupies 230µ m × 45µ m of area. Furthermore, a wide band TIA is designed using the matching technique. It is shown that by simultaneously using of series input matching topology and T-output matching network, the bandwidth of the TIA can be obviously improved. This methodology is supported by a design example in a 0.18 µ m CMOS technology. The post layout simulation results show a bandwidth of 20 GH z with 50 f F photodiode capacitance, a transimpedance gain of 52.6 dBΩ, 11 pA/√H z input referred noise and group delay less than 8.3 ps. The TIA dissipates 1.3 mW from a 1.8 V supply voltage. In addition, a new design possessing to extend the bandwidth of the TIA is presented. This TIA employs a parallel combination of two series resonate circuits with different resonate frequencies on the conventional regulated common gate (RGC) architecture. In the proposed TIA, a capacitance degeneration and series inductive peaking technique are used for pole-zero elimination. The TIA is implemented in a 0.18 µ m CMOS process, where a 100 f F photodiode is considered. The post layout simulation results show a transimpedance gain of 53 dBΩ transimpedance gain along with a 13 GH z bandwidth. The designed TIA consumes 11 mW from a 1.8 V supply, and its group-delay variation is 5 ps with 24 pA/√H z input referred noise. xxii In the last phase of the work, a technique to enhance the bandwidth of the regulated common gate (RCG) transimpedance amplifier is described. The technique is based on using a cascode current mirror with resistive compensation technique and a ladder matching network. In order to verify the operation and the performance of the proposed technique, a CMOS design example is designed using the 0.18µ m CMOS process technology. The post layout simulation results show that, the proposed TIA achieved a bandwidth of 8.4 GH z, a transimpedance gain of 51.3 dBΩ and input referred noise current spectral density of 20 pA/√H z. The average group-delay variation is 4 ps over the bandwidth and the TIA consumes 17.8 mW from a 1.8 V supply. To sum up, this thesis focuses on various design techniques of transimpedance amplifier (TIA) that improves the bandwidth performance. We believe that, our approaches and techniques exhibit a path which other future researchers can follow and as well refer to as their researching domain and also could be used in their research applications.DoktoraPh

Adaptive Suppression of Interfering Signals in Communication Systems

The growth in the number of wireless devices and applications underscores the need for characterizing and mitigating interference induced problems such as distortion and blocking. A typical interference scenario involves the detection of a small amplitude signal of interest (SOI) in the presence of a large amplitude interfering signal; it is desirable to attenuate the interfering signal while preserving the integrity of SOI and an appropriate dynamic range. If the frequency of the interfering signal varies or is unknown, an adaptive notch function must be applied in order to maintain adequate attenuation. This work explores the performance space of a phase cancellation technique used in implementing the desired notch function for communication systems in the 1-3 GHz frequency range. A system level model constructed with MATLAB and related simulation results assist in building the theoretical foundation for setting performance bounds on the implemented solution and deriving hardware specifications for the RF notch subsystem devices. Simulations and measurements are presented for a Low Noise Amplifer (LNA), voltage variable attenuators, bandpass filters and phase shifters. Ultimately, full system tests provide a measure of merit for this work as well as invaluable lessons learned. The emphasis of this project is the on-wafer LNA measurements, dependence of IC system performance on mismatches and overall system performance tests. Where possible, predictions are plotted alongside measured data. The reasonable match between the two validates system and component models and more than compensates for the painstaking modeling efforts. Most importantly, using the signal to interferer ratio (SIR) as a figure of merit, experimental results demonstrate up to 58 dB of SIR improvement. This number represents a remarkable advancement in interference rejection at RF or microwave frequencies