Flexible Receivers in CMOS for Wireless Communication

Consumers are pushing for higher data rates to support more services that are introduced in mobile applications. As an example, a few years ago video-on-demand was only accessed through landlines, but today wireless devices are frequently used to stream video. To support this, more flexible network solutions have merged in 4G, introducing new technical problems to the mobile terminal. New techniques are thus needed, and this dissertation explores five different ideas for receiver front-ends, that are cost-efficient and flexible both in performance and operating frequency. All ideas have been implemented in chips fabricated in 65 nm CMOS technology and verified by measurements. Paper I explores a voltage-mode receiver front-end where sub-threshold positive feedback transistors are introduced to increase the linearity in combination with a bootstrapped passive mixer. Paper II builds on the idea of 8-phase harmonic rejection, but simplifies it to a 6-phase solution that can reject noise and interferers at the 3rd order harmonic of the local oscillator frequency. This provides a good trade-off between the traditional quadrature mixer and the 8- phase harmonic rejection mixer. Furthermore, a very compact inductor-less low noise amplifier is introduced. Paper III investigates the use of global negative feedback in a receiver front-end, and also introduces an auxiliary path that can cancel noise from the main path. In paper IV, another global feedback based receiver front-end is designed, but with positive feedback instead of negative. By introducing global positive feedback, the resistance of the transistors in a passive mixer-first receiver front-end can be reduced to achieve a lower noise figure, while still maintaining input matching. Finally, paper V introduces a full receiver chain with a single-ended to differential LNA, current-mode downconversion mixers, and a baseband circuity that merges the functionalities of the transimpedance amplifier, channel-select filter, and analog-to-digital converter into one single power-efficient block

A wideband blocker-resilient RF front-end with selective input-impedance matching for direct-ΔΣ-receiver architectures

This paper presents a wideband blocker-tolerant RF front-end suitable for direct-ΔΣ-E-receivers. Blockers are attenuated by providing low receiver input impedance at blocker frequencies while for desired frequency the input impedance is boosted to matched condition by providing an up-converted positive feedback from the baseband stage. RF front-end is evaluated on 28nm fully-depleted silicon-on-insulator CMOS process with current consumption of 8mA, excluding local-oscillator drive, at 1V supply voltage. Front-end is reconfigurable from 0.7-3GHz with maximum noise figure of 5dB and achieves an out-of-band 1dB compression point of 0dBm at 100MHz local oscillator frequency offset.Peer reviewe