24 research outputs found
Design And Implementation Of Up-Conversion Mixer And Lc-Quadrature Oscillator For IEEE 802.11a WLAN Transmitter Application Utilizing 0.18 Pm CMOS Technology [TK7871.99.M44 H279 2008 f rb].
Perlumbaan implementasi litar terkamil radio, dengan kos yang rendah telah menggalakkan penggunaan teknologi CMOS.
The drive for cost reduction has led to the use of CMOS technology for highly integrated radios
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Integrated circuits for efficient power delivery using pulse-width-modulation
Circuits and architectures for efficient power delivery have become crucial in emerging smart systems. Switching power amplifiers (PA) are very attractive for such applications, because they exhibit better efficiency compared to linear PA designs, due to saturated operation. Switching PAs also allow for utilization of deep submicron CMOS technologies, due to which these designs can be easily integrated with digital circuits, and can benefit from process scaling, in performance as well as in area.
Pulse-width-modulation (PWM) is commonly used with switching PAs. A PWM signal typically employs a high-frequency switching pulse waveform as a carrier signal, wherein the pulse-width or duty-cycle of each pulse is modulated by a given low-frequency input signal. The carrier frequency can vary from several kHz to GHz, and is typically determined by the target application.
In this thesis, efficient power-delivery circuits that use PWM with switching class-D stages are presented. Advanced circuit techniques, as well as architectures for PWM are proposed to enhance efficiency and circumvent the limitations of conventional architectures.
A digitally-intensive transmitter using RF-PWM with a class-D PA is described in the first part of the thesis. The use of carrier switching for alleviating the dynamic range limitation that can be observed in classical RF-PWM implementations is introduced. The approach employs the full carrier frequency for half of the amplitude range, and the second harmonic of half of the carrier frequency, for the remainder of the amplitude range. This concept not only allows the transmitter to drive modulated signals with large peak-to-average power ratio (PAPR), but also improves the back-off efficiency due to reduced switching losses in the half carrier-frequency mode. A glitch-free phase selector is proposed that removes the deleterious glitches that can occur at the input data transitions. The phase-selector also prevents D flip-flop setup-and-hold time violations. The transmitter has been implemented in a 130-nm CMOS process. The measured peak output power and power-added-efficiency (PAE) are 25.6 dBm and 34%, respectively. While driving 802.11g 20-MHz 64-QAM OFDM signals, the average measured output power is 18.3 dBm and the PAE is 16%, with an EVM of -25.5 dB.
The second part of the thesis describes a high-speed driver that provides a PWM output using a class-D PA. A PLL-based architecture is employed which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which are typically used for PWM generation. Multi-level signaling is proposed to enhance back-off as well as peak efficiency, which is critical for signals with high PAPR. A differential, folded PWM scheme is introduced to achieve highly linear operation. 3-level operation is achieved without the requirement for additional supply source or sink paths, while 5-level operation is achieved with additional supply source and sink paths, compared to 2-level operation. The PWM driver has been implemented in a 130-nm CMOS process and can operate with a switching frequency of 40-to-170 MHz. For 2/3/5-level PA operation, with a 500 kHz sinusoidal input and 60 MHz switching frequency, the measured THD is -61/-62/-53 dB and corresponding efficiency is 71/83/86% with 175/200/220 mW output power level, respectively. Performance has also been verified for 2/3-level PA operation with a high PAPR signal with 500 kHz bandwidth. While intended as a general purpose amplifier, the approach is well-suited for applications such as power-line communications (PLC).
The final part of the thesis introduces an efficient buck/buck-boost reconfigurable LED driver that supports PWM and PFM operation. The driver is based on peak current control. Rectified sin as well as sin² functions are employed in the reference signal to improve the power factor (PF) and total harmonic distortion (THD) of the buck and buck-boost converters. The design ensures that the peak of the inductor current maintains a constant level that is invariant for different AC line voltages. The operating mode of the design can be changed between PWM and PFM. The LED driver has been implemented in a 130-nm CMOS process. PF and THD are improved when the proposed reference is employed, and peak PF and lowest THD are 0.995/0.983/0.996 and 7.8/6.2/3.5% for the buck (PWM), buck (PFM), buck-boost (PFM) cases, respectively. The corresponding peak efficiency for the three cases is 88/92/91%, respectively.Electrical and Computer Engineerin
Low Power Circuit Design in Sustainable Self Powered Systems for IoT Applications
The Internet-of-Things (IoT) network is being vigorously pushed forward from many fronts in
diverse research communities. Many problems are still there to be solved, and challenges are found
among its many levels of abstraction. In this thesis we give an overview of recent developments
in circuit design for ultra-low power transceivers and energy harvesting management units for the
IoT.
The first part of the dissertation conducts a study of energy harvesting interfaces and optimizing
power extraction, followed by power management for energy storage and supply regulation. we
give an overview of the recent developments in circuit design for ultra-low power management
units, focusing mainly in the architectures and techniques required for energy harvesting from
multiple heterogeneous sources. Three projects are presented in this area to reach a solution that
provides reliable continuous operation for IoT sensor nodes in the presence of one or more natural
energy sources to harvest from.
The second part focuses on wireless transmission, To reduce the power consumption and boost
the Tx energy efficiency, a novel delay cell exploiting current reuse is used in a ring-oscillator
employed as the local oscillator generator scheme. In combination with an edge-combiner power
amplifier, the Tx showed a measured energy efficiency of 0.2 nJ=bit and a normalized energy
efficiency of 3.1 nJ=bit:mW when operating at output power levels up to -10 dBm and data rates
of 3 Mbps
Advanced CMOS Integrated Circuit Design and Application
The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems
Receiver Front-Ends in CMOS with Ultra-Low Power Consumption
Historically, research on radio communication has focused on improving range and data rate. In the last decade, however, there has been an increasing demand for low power and low cost radios that can provide connectivity with small devices around us. They should be able to offer basic connectivity with a power consumption low enough to function extended periods of time on a single battery charge, or even energy scavenged from the surroundings. This work is focused on the design of ultra-low power receiver front-ends intended for a receiver operating in the 2.4GHz ISM band, having an active power consumption of 1mW and chip area of 1mm². Low power consumption and small size make it hard to achieve good sensitivity and tolerance to interference. This thesis starts with an introduction to the overall receiver specifications, low power radio and radio standards, front-end and LO generation architectures and building blocks, followed by the four included papers. Paper I demonstrates an inductorless front-end operating at 915MHz, including a frequency divider for quadrature LO generation. An LO generator operating at 2.4GHz is shown in Paper II, enabling a front-end operating above 2GHz. Papers III and IV contain circuits with combined front-end and LO generator operating at or above the full 2.45GHz target frequency. They use VCO and frequency divider topologies that offer efficient operation and low quadrature error. An efficient passive-mixer design with improved suppression of interference, enables an LNA-less design in Paper IV capable of operating without a SAW-filter
System and Circuit Design Techniques for Silicon-based Multi-band/Multi-standard Receivers
Today, the advances in Complementary MetalOxideSemiconductor (CMOS)
technology have guided the progress in the wireless communications circuits and
systems area. Various new communication standards have been developed to accommodate
a variety of applications at different frequency bands, such as cellular
communications at 900 and 1800 MHz, global positioning system (GPS) at 1.2 and
1.5 GHz, and Bluetooth andWiFi at 2.4 and 5.2 GHz, respectively. The modern wireless
technology is now motivated by the global trend of developing multi-band/multistandard
terminals for low-cost and multifunction transceivers. Exploring the unused
10-66 GHz frequency spectrum for high data rate communication is also another trend
in the wireless industry.
In this dissertation, the challenges and solutions for designing a multi-band/multistandard
mobile device is addressed from system-level analysis to circuit implementation.
A systematic system-level design methodology for block-level budgeting is
proposed. The system-level design methodology focuses on minimizing the power
consumption of the overall receiver. Then, a novel millimeter-wave dual-band receiver
front-end architecture is developed to operate at 24 and 31 GHz. The receiver
relies on a newly introduced concept of harmonic selection that helps to reduce the complexity of the dual-band receiver. Wideband circuit techniques for millimeterwave
frequencies are also investigated and new bandwidth extension techniques are
proposed for the dual-band 24/31 GHz receiver. These new techniques are applied
for the low noise amplifier and millimeter-wave mixer resulting in the widest reported
operating bandwidth in K-band, while consuming less power consumption.
Additionally, various receiver building blocks, such as a low noise amplifier with
reconfigurable input matching network for multi-band receivers, and a low drop-out
regulator with high power supply rejection are analyzed and proposed. The low
noise amplifier presents the first one with continuously reconfigurable input matching
network, while achieving a noise figure comparable to the wideband techniques. The
low drop-out regulator presented the first one with high power supply rejection in the
mega-hertz frequency range.
All the proposed building blocks and architecture in this dissertation are implemented
using the existing silicon-based technologies, and resulted in several publications
in IEEE Journals and Conferences
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Power-efficient Circuit Architectures for Receivers Leveraging Nanoscale CMOS
Cellular and mobile communication markets, together with CMOS technology scaling, have made complex systems-on-chip integrated circuits (ICs) ubiquitous. Moving towards the internet of things that aims to extend this further requires ultra-low power and efficient radio communication that continues to take advantage of nanoscale CMOS processes. At the heart of this lie orthogonal challenges in both system and circuit architectures of current day technology.
By enabling transceivers at center frequencies ranging in several tens of GHz, modern CMOS processes support bandwidths of up to several GHz. However, conventional narrowband architectures cannot directly translate or trade-off these speeds to lower power consumption. Pulse-radio UWB (PR-UWB), a fundamentally different system of communication enables this trade-off by bit-level duty-cycling i.e., power-gating and has emerged as an alternative to conventional narrowband systems to achieve better energy efficiency. However, system-level challenges in the implementation of transceiver synchronization and duty-cycling have remained an open challenge to realize the ultra-low power numbers that PR-UWB promises. Orthogonally, as CMOS scaling continues,
approaching 28nm and 14nm in production digital processes, the key transistor characteristics have rapidly changed. Changes in supply voltage, intrinsic gain and switching speeds have rendered conventional analog circuit design techniques obsolete, since they do not scale well with the digital backend engines that dictate scaling. Consequently, circuit architectures that employ time-domain processing and leverage the faster switching speeds have become attractive. However, they are fundamentally limited by their inability to support linear domain-to-domain conversion and hence, have remained un-suited to high-performance applications.
Addressing these requirements in different dimensions, two pulse-radio UWB receiver and a continuous-time filter silicon prototypes are presented in this work. The receiver prototypes focus on system level innovation while the filter serves as a demonstration vehicle for novel circuit architectures developed in this work. The PR-UWB receiver prototypes are implemented in a 65nm LP CMOS technology and are fully integrated solutions. The first receiver prototype is a compact UWB receiver front end operating at 4.85GHz that is aggressively duty-cycled. It occupies an active area of only 0.4 mm², thanks to the use of few inductors and RF G_m-C filters and incorporates an automatic-threshold-recovery-based demodulator for digitization. The prototype achieves a sensitivity of -88dBm at a data rate of 1Mbps (for a BER of 10^-3), while achieving the lowest energy consumption gradient (dP/df_data=450pJ/bit) amongst other receivers operating in the lower UWB band, for the same sensitivity.
However, this prototype is limited by idle-time power consumption (e.g., bias) and lacks synchronization capability. A fully self-duty-cycled and synchronized UWB pulse-radio receiver SoC targeted at low-data-rate communication is
presented as the second prototype. The proposed architecture builds on the automatic-threshold-recovery-based demodulator to achieve synchronization using an all-digital clock and data recovery loop. The SoC synchronizes with the incoming pulse stream from the transmitter and duty-cycles itself. The SoC prototype achieves a -79.5dBm, 1Mbps-normalized sensitivity for a >5X improvement over the state of the art in power consumption (375pJ/bit), thanks to aggressive signal path and bias circuit duty-cycling. The SoC is fully integrated to achieve RF-in to bit-out operation and can interface with off-chip, low speed digital components.
Finally, switched-mode signal processing, a signal processing paradigm that enables the design of highly linear, power-efficient feedback amplifiers is presented. A 0.6V continuous-time filter prototype that demonstrates the advantages of this technique is presented in a 65nm GP CMOS process. The filter draws 26.2mW from the supply while operating at a full-scale that is 73% of the V_dd, a bandwidth of 70MHz and a peak signal-to-noise-and-distortion ratio (SNDR) of 55.8dB. This represents a 2-fold improvement in full-scale and a 10-fold improvement in the bandwidth over state-of-the-art filter implementations, while demonstrating excellent linearity and signal-to-noise ratio. To sum up, innovations spanning both system and circuit architectures that leverage the speeds of nanoscale CMOS processes to enable power-efficient solutions to next-generation wireless receivers are presented in this work
High Performance LNAs and Mixers for Direct Conversion Receivers in BiCMOS and CMOS Technologies
The trend in cellular chipset design today is to incorporate support for a larger number of frequency bands for each new chipset generation. If the chipset also supports receiver diversity two low noise amplifiers (LNAs) are required for each frequency band. This is however associated with an increase of off-chip components, i.e. matching components for the LNA inputs, as well as complex routing of the RF input signals. If balanced LNAs are implemented the routing complexity is further increased. The first presented work in this thesis is a novel multiband low noise single ended LNA and mixer architecture. The mixer has a novel feedback loop suppressing both second order distortion as well as DC-offset. The performance, verified by Monte Carlo simulations, is sufficient for a WCDMA application. The second presented work is a single ended multiband LNA with programmable integrated matching. The LNA is connected to an on-chip tunable balun generating differential RF signals for a differential mixer. The combination of the narrow band input matching and narrow band balun of the presented LNA is beneficial for suppressing third harmonic downconversion of a WLAN interferer. The single ended architecture has great advantages regarding PCB routing of the RF input signals but is on the other hand more sensitive to common mode interferers, e.g. ground, supply and substrate noise. An analysis of direct conversion receiver requirements is presented together with an overview of different LNA and mixer architectures in both BiCMOS and CMOS technology
Projeto de Malha de Captura de Fase Autocalibrável
O impacto das variações de processo e desvios "intra-die" no fabrico de circuitos analógicos e de sinal misto (AMS), nomeadamente no rendimento do fabrico, em custos e confiança, tornaram-se críticos com a adoção de tecnologias MOS sub- micrométricas. Quando em operação, a sensibilidade dos circuitos a grandezas ambientais, como temperatura, tensão e interferências de outros blocos, gera novas fontes de variabilidade. Perante estes desvios, circuitos de alto desempenho requerem a integração de metodologias de calibração que facilitem a correção dos parâmetros de desempenho após fabrico e o ajuste dos mesmos quando em operação. Este circuito adicional pode representar uma pequena fração adicional da área total de circuito e da potência consumida, mas ainda assim pode resultar mais eficiente em área e energia do que qualquer sobredimensionamento analógico ou processo auxiliar puramente digital de detecção e correção.The impacts of process variations and intra-die device mismatches of analog and mixed-signal (AMS) circuits, namely regarding fabrication yield, costs, and reliability have become critical with the adoption of deep sub-micron MOS technologies. When in operation, circuits' sensitivity to environmental quantities, such as temperature, voltage, as well as interferences originating from other blocks, render new sources of variability. High performance circuits require the adoption of built-in calibration and test facilities which facilitate tuning performance parameters after fabrication and correcting them when in operation. This extra added circuitry may represent a small fraction of total circuit area and power, but still it may be more area- and power- efficient than either analog "overdesign" or purely digital detection and correction
Stratégie d'alimentation pour les SoCs RF très faible consommation
Les réseaux de capteurs sans fil nécessitent des fonctions de calcul et de transmissionradio associées à chaque capteur. Les SoCs RF intégrant ces fonctions doivent avoir uneautonomie la plus grande possible et donc une très faible consommation. Aujourd'hui, leursperformances énergétiques pourraient être fortement améliorées par des systèmes d'alimentationinnovants. En effet, les circuits d'alimentation remplissent leur fonction classique de conversiond'énergie mais aussi des fonctions d'isolation des blocs RF et digitaux. Leurs performancess'évaluent donc en termes d'efficacité énergétique et de réponse transitoire mais aussi d'isolationentre blocs et de réjection de bruit.Ce travail de thèse concerne l'intégration du système de gestion et de distribution del énergie aux différents blocs RF d un émetteur/récepteur en élaborant une méthodologie topdown pour déterminer la sensibilité de chaque bloc à son alimentation et en construisant unearchitecture innovante et dynamique de gestion/distribution de l'énergie sur le SoC. Cetteméthodologie repose sur la disponibilité de régulateurs de tension présentant des performancesadaptées. Un deuxième volet du travail de thèse a donc été de réaliser un régulateur linéaire detype LDO à forte réjection sur une bande passante relativement large et bien adapté àl'alimentation de blocs RF très sensibles aux bruits de l'alimentation.Wireless sensor networks require calculation functions and radiofrequencytransmission modules within each sensor. RF SoCs integrating these functions must have thebiggest battery life and so a very small consumption. Today, innovative power managementsystems could highly enhance the energy performances of this type of RF SoC. Indeed, thesepower systems perform energy conversion and also the isolation functions of RF and digitalblocks. Their features are thus estimated in terms of energy efficiency, transient response and alsoisolation between blocks and noise rejection.This thesis work concerns the integration of the power management systems and itsdistribution channels into different ultra-low-power SoCs. This was achieved mainly thanks to thedevelopment of a new top-down approach. This new methodology consists of determining thesensibility of every block to its power supply and of designing an innovative and dynamicarchitecture of power management circuits on the SoC. This study ends up in the implementationof a very efficient low dropout (LDO) regulator for noise-sensitive low-current RF blocks inmixed SoC applications. The fabricated prototype achieves a high power supply rejection for awide range of frequencies.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF