Stabilization of self-mode-locked quantum dash lasers by symmetric dual-loop optical feedback

We report experimental studies of the influence of symmetric dual-loop optical feedback on the RF linewidth and timing jitter of self-mode-locked two-section quantum dash lasers emitting at 1550 nm. Various feedback schemes were investigated and optimum levels determined for narrowest RF linewidth and low timing jitter, for single-loop and symmetric dual-loop feedback. Two symmetric dual-loop configurations, with balanced and unbalanced feedback ratios, were studied. We demonstrate that unbalanced symmetric dual loop feedback, with the inner cavity resonant and fine delay tuning of the outer loop, gives the narrowest RF linewidth and reduced timing jitter over a wide range of delay, unlike single and balanced symmetric dual-loop configurations. This configuration with feedback lengths of 80 and 140 m narrows the RF linewidth by ∼ 4–67x and ∼ 10–100x, respectively, across the widest delay range, compared to free-running. For symmetric dual-loop feedback, the influence of different power split ratios through the feedback loops was determined. Our results show that symmetric dual-loop feedback is markedly more effective than single-loop feedback in reducing RF linewidth and timing jitter, and is much less sensitive to delay phase, making this technique ideal for applications where robustness and alignment tolerance are essential

Stabilisation of self mode-locked quantum dash semiconductor lasers

Semiconductor mode-locked lasers are compact pulsed sources which produce high quality optical pulses with high repetition rates and subpicosecond pulse duration. In order to use these sources in real applications, low timing jitter and robust feedback control stabilisation is highly desirable. In this thesis, a series of experimental studies have been performed to achieve stabilisation of two-section self mode-locked quantum-dash laser emitting at ∼ 1.55 µm and operating at 21 GHz repetition rate. First, stabilisation of self mode-locked quantum-dash laser over a wide range of delay tuning was achieved using symmetric dual-loop feedback. Optimum levels were determined for narrowest RF linewidth and reduced timing jitter for single- and symmetric dual-loop feedback. Two symmetric dual-loop configurations, with balanced and unbalanced feedback ratios, were studied. We have demonstrated unbalanced symmetric dual-loop feedback, with the inner cavity resonant and fine delay tuning of the outer loop, produced narrowest RF linewidth and reduced timing jitter over a wide range of delay, unlike single and balanced symmetric dual-loop configurations. This configuration with feedback lengths 80 and 140 m reduced the RF linewidth by ∼ 4-67x (∼ 2-9x timing jitter reduction) and ∼ 10-100x (∼ 2.5-10x timing jitter reduction), respectively, across the widest delay range, compared to free-running. For symmetric dual-loop feedback, the influence of different power split ratios through the feedback loops was also determined. We achieved the optimum stabilisation of self mode-locked quantum-dash laser over a wide range of delay tuning using asymmetric dual-loop feedback. Various feedback schemes were investigated and feedback levels far narrowest RF linewidth and low timing jitter were identified, for single- and asymmetric dual-loop feedback. We demonstrated that asymmetric dual-loop feedback, with the shorter feedback cavity tuned to be fully resonant, followed by fine-tuning of the phase of the longer feedback cavity, gave stable narrow RF spectra across the widest delay range, unlike single-loop feedback and free-running conditions. This asymmetric dual-loop scheme reduced the RF linewidth ∼ 2.5-4x compared to single-loop and ∼ 4-100x relative to free-running conditions. In addition, for asymmetric dual-loop feedback, significant suppression in fundamental side-mode was achieved relative to single-loop feedback. In addition, we have demonstrated an asymmetric dual-loop feedback scheme to suppress external cavity side-modes induced in self mode-locked quantum-dash lasers with conventional single- and dual-loop feedback. We reported optimal suppression of spurious tones by optimising the delay in the second loop. We observed that asymmetric dual-loop feedback, with large (∼ 8x) disparity in loop lengths, produced significant suppression in external-cavity side-modes and yielded flat RF spectra close to the main peak with low timing jitter, compared to single-loop feedback. Significant reduction in RF linewidth and reduced timing jitter was also produced by optimising delay time in the second feedback loop. Experimental results based on this feedback configuration validate predictions of recently published numerical simulations. Finally, we reported stabilisation of our self mode-locked quantum-dash laser on the widest range of delay tuning using simultaneous continuous-wave optical injection and optical feedback. With optical injection, various wavelength detuning ranges (1568 to 1578 nm) and optimum wavelengths (1571.725 to 1572.710) were determined which yielded narrowest RF linewidth and reduced timing jitter. We demonstrated that under double resonance, with both optical feedback and continuous-wave injection, a minimum RF linewidth of 100x lower than the free-running condition

Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage

A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD-CP Noise Is not multiplied by N^2

This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 X 0.45 m

Analysis and equalization of data-dependent jitter

Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10/sup -12/ BER from 30 to 52 ps at 10 Gb/s

Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications

Programmable rate modem utilizing digital signal processing techniques

The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery

A PLL Exploiting Sub-Sampling of the VCO Output to Reduce In-band Phase Noise

Abstract— In this paper, we present a 2.2-GHz low jitter PLL based on sub-sampling. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. A frequency locked loop guarantees correct frequency locking without degenerating jitter performance. The PLL implemented in a standard 0.18-μm CMOS process consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 × 0.45 mm2. The in-band phase noise at 200 kHz offset is measured to be -126 dBc/Hz and the rms PLL output jitter integrated from 10 kHz to 40 MHz is 0.15 ps