Design of a low jitter digital PLL with low input frequency

Complex digital circuits such as microprocessors typically require support circuitry that has traditionally been realized using analog or mixed-signal macros. PLL circuits are used in many integrated applications such as frequency synthesizers and inter-chip communication interfaces. As process technologies advance and grow in complexity, the challenge of maintaining required analog elements and performance for use in circuits such as PLLs grows. Recently, digital PLL (DPLL) has emerged as an alternative to analog PLL to overcome many constraints such as low supply voltage, poor analog transistor behavior, larger area due to integrated capacitor and process variability. However, DPLLs have high deterministic jitter due to quantization noise of time-to-digital converter (TDC) and digitally-controlled oscillator (DCO) and struggle with random jitter of oscillator. In this thesis, hybrid analog/digital proportional/integral control is used to suppress TDC quantization error and digital phase accumulation techniques to mitigate DCO quantization error. VCO phase noise was reduced using an embedded voltage-mode feedback. This feedback loop is implemented by using a switched-C circuit which converts frequency to current. Designed in a 130nm CMOS process, the proposed DPLL generates more than 1GHz output frequency with low input frequency and achieves superior jitter performance compared to conventional DPLL in simulations

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

Quadrature Phase-Domain ADPLL with Integrated On-line Amplitude Locked Loop Calibration for 5G Multi-band Applications

5th generation wireless systems (5G) have expanded frequency band coverage with the low-band 5G and mid-band 5G frequencies spanning 600 MHz to 4 GHz spectrum. This dissertation focuses on a microelectronic implementation of CMOS 65 nm design of an All-Digital Phase Lock Loop (ADPLL), which is a critical component for advanced 5G wireless transceivers. The ADPLL is designed to operate in the frequency bands of 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz. Unique ADPLL sub-components include: 1) Digital Phase Frequency Detector, 2) Digital Loop Filter, 3) Channel Bank Select Circuit, and 4) Digital Control Oscillator. Integrated with the ADPLL is a 90-degree active RC-CR phase shifter with on-line amplitude locked loop (ALL) calibration to facilitate enhanced image rejection while mitigating the effects of fabrication process variations and component mismatch. A unique high-sensitivity high-speed dynamic voltage comparator is included as a key component of the active phase shifter/ALL calibration subsystem. 65nm CMOS technology circuit designs are included for the ADPLL and active phase shifter with simulation performance assessments. Phase noise results for 1 MHz offset with carrier frequencies of 600MHz, 2.4GHz, and 3.8GHz are -130, -122, and -116 dBc/Hz, respectively. Monte Carlo simulations to account for process variations/component mismatch show that the active phase shifter with ALL calibration maintains accurate quadrature phase outputs when operating within the frequency bands 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz

Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters

In this dissertation, time-based signal processing techniques and their applications in oversampling and noise-shaping data converters are examined. These techniques demonstrate the ability to shift the burden of high performance analog circuits from the compressed voltage-domain to the augmented time-domain. First, the potential of high order noise-shaping and phase-domain feedback in time-to-digital converters (TDCs) is explored. A prototype phase reference, second-order continuous-time delta-sigma TDC for sensor applications was fabricated in 90nm CMOS and achieves 64 dB dynamic range in 1MHz signal bandwidth. Second, an ultra-high performance oscillator-based delta-sigma modulator architecture is investigated. The proposed circuit is a third-order continuous-time PLL-Based Delta-Sigma Modulator with simulated 77 dB SNDR in 40MHz signal bandwidth with OSR of 16, and is fabricated in 65nm CMOS

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

Performance enhancement techniques for low power digital phase locked loops

Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions. In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques

Efficient Continuous-Time Sigma-Delta Converters for High Frequency Applications

Over the years Continuous-Time (CT) Sigma-Delta (ΣΔ) modulators have received a lot of attention due to their ability to efficiently digitize a variety of signals, and suitability for many different applications. Because of their tolerance to component mismatch, the easy to drive input structure, as well as intrinsic anti-aliasing filtering and noise shaping abilities, CTΣΔ modulators have become one of the most popular data-converter type for high dynamic range and moderate/wide bandwidth. This trend is the result of faster CMOS technologies along with design innovations such as better architectures and faster amplifiers. In other words, CTΣΔ modulators are starting to offer the best of both worlds, with high resolution and high bandwidth. This dissertation focuses on the bandwidth and resolution of CTΣΔ modulators. The goal of this research is to use the noise shaping benefits of CTΣΔ modulators for different wireless applications, while achieving high resolution and/or wide bandwidth. For this purpose, this research focuses on two different application areas that demand speed and resolution. These are a low-noise high-resolution time-to-digital converter (TDC), ideal for digital phase lock loops (PLL), and a very high-speed, wide-bandwidth CTΣΔ modulator for wireless communication. The first part of this dissertation presents a new noise shaping time-to-digital converter, based on a CTΣΔ modulator. This is intended to reduce the in-band phase noise of a high frequency digital phase lock loop (PLL) without reducing its loop bandwidth. To prove the effectiveness of the proposed TDC, 30GHz and a 40GHz fractional-N digital PLL are designed as a signal sources for a 240GHz FMCW radar system. Both prototypes are fabricated in a 65nm CMOS process. The standalone TDC achieves 81dB dynamic range and 13.2 equivalent number of bits (ENOB) with 176fs integrated-rms noise from 1MHz bandwidth. The in-band phase noise of the 30GHz digital fractional-N PLL is measured as -87dBc/Hz at a 100kHz offset which is equivalent to -212.6dBc/Hz2 normalized in-band phase noise. The second part of this dissertation focuses on high-speed (GS/s) CTΣΔ modulators for wireless communication, and introduces a new time-interleaved reference data weighted averaging (TI-RDWA) architecture suitable for GS/s CTΣΔ modulators. This new architecture shapes the digital-to-analog converter (DAC) mismatch effects in a CTΣΔ modulator at GS/s operating speeds. It allows us to use smaller DAC unit sizes to reduce area and power consumption for the same bandwidth. The prototype 5GS/s CTΣΔ modulator with TI-RDWA is fabricated in 40nm CMOS and it achieves 156MHz bandwidth, 70dB dynamic range, 84dB SFDR and a Schreier FoM of 158.3dB.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138763/1/bdayanik_1.pd

Low power VCO-based analog-to-digital conversion

textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin

A digital multiplying delay locked loop for high frequency clock generation

As Moore’s Law continues to give rise to ever shrinking channel lengths, circuits are becoming more digital and ever increasingly faster. Generating high frequency clocks in such scaled processes is becoming a tough challenge. Digital phase locked loops (DPLLs) are being explored as an alternative to conventional analog PLLs but suffer from issues such as low bandwidth and higher quantization noise. A digital multiplying delay locked loop (DMDLL) is proposed which aims at leveraging the benefit of high bandwidth of DLL while at the same time achieving the frequency multiplication property of PLL. It also offers the benefits of easier portability across process and occupies lesser area. The proposed DMDLL uses a simple flip-flop as 1-bit TDC (Time Digital Converter) for Phase Detector (PD). A digital accumulator acts as integrator for loop filter while a Δ-Σ DAC in combination with a VCO acts like a DCO. A carefully designed select logic in conjunction with a MUX achieves frequency multiplication. The proposed digital MDLL is taped out in 130nm process and tested to obtain 1.4GHz output frequency with 1.6ps RMS jitter, 17ps peak-to-peak jitter and -50dbC/Hz reference spurs