On the Design of Power Law Filters and Their Inverse Counterparts

This paper presents the optimal modeling of Power Law Filters (PLFs) with the low-pass (LP), high-pass (HP), band-pass (BP), and band-stop (BS) responses by means of rational approximants. The optimization is performed for three different objective functions and second-order filter mother functions. The formulated design constraints help avoid placement of the zeros and poles on the right-half s-plane, thus, yielding stable PLF and inverse PLF (IPLF) models. The performances of the approximants exhibiting the fractional-step magnitude and phase responses are evaluated using various statistical indices. At the cost of higher computational complexity, the proposed approach achieved improved accuracy with guaranteed stability when compared to the published literature. The four types of optimal PLFs and IPLFs with an exponent alpha of 0.5 are implemented using the follow-the-leader feedback topology employing AD844AN current feedback operational amplifiers. The experimental results demonstrate that the Total Harmonic Distortion achieved for all the practical PLF and IPLF circuits was equal or lower than 0.21%, whereas the Spurious-Free Dynamic Range also exceeded 57.23 and 54.72 dBc, respectively

Reconnection–less Reconfigurable Fractional–Order Current–Mode Integrator Design with Simple Control

A design of a fractional-order (FO) integrator is introduced for operation of resulting solution in the current mode (CM). The solution of the integrator is based on the utilization of RC structures, but in comparison to other RC structure based FO designs, the proposed integrator offers the electronic control of the order. Moreover, the control of the proposed integrator does not require multiple specific and accurate values of the control voltages/currents in comparison to the topologies based on the approximation of the FO Laplacian operator. The electronic control of a gain level (gain adjustment) of the proposed integrator is available. The paper offers the results of Cadence IC6 (spectre) simulations and more importantly experimental measurements to support the presented design. The proposed integrator can be used to build various FO circuits as demonstrated by the utilization of the integrator into a structure of a frequency filter in order to provide FO characteristics

Analog Implementation of Fractional-Order Elements and Their Applications

With advancements in the theory of fractional calculus and also with widespread engineering application of fractional-order systems, analog implementation of fractional-order integrators and differentiators have received considerable attention. This is due to the fact that this powerful mathematical tool allows us to describe and model a real-world phenomenon more accurately than via classical “integer” methods. Moreover, their additional degree of freedom allows researchers to design accurate and more robust systems that would be impractical or impossible to implement with conventional capacitors. Throughout this thesis, a wide range of problems associated with analog circuit design of fractional-order systems are covered: passive component optimization of resistive-capacitive and resistive-inductive type fractional-order elements, realization of active fractional-order capacitors (FOCs), analog implementation of fractional-order integrators, robust fractional-order proportional-integral control design, investigation of different materials for FOC fabrication having ultra-wide frequency band, low phase error, possible low- and high-frequency realization of fractional-order oscillators in analog domain, mathematical and experimental study of solid-state FOCs in series-, parallel- and interconnected circuit networks. Consequently, the proposed approaches in this thesis are important considerations in beyond the future studies of fractional dynamic systems

Circuits for Analog Signal Processing Employing Unconventional Active Elements

Disertační práce se zabývá zaváděním nových struktur moderních aktivních prvků pracujících v napěťovém, proudovém a smíšeném režimu. Funkčnost a chování těchto prvků byly ověřeny prostřednictvím SPICE simulací. V této práci je zahrnuta řada simulací, které dokazují přesnost a dobré vlastnosti těchto prvků, přičemž velký důraz byl kladen na to, aby tyto prvky byly schopny pracovat při nízkém napájecím napětí, jelikož poptávka po přenosných elektronických zařízeních a implantabilních zdravotnických přístrojích stále roste. Tyto přístroje jsou napájeny bateriemi a k tomu, aby byla prodloužena jejich životnost, trend navrhování analogových obvodů směřuje k stále většímu snižování spotřeby a napájecího napětí. Hlavním přínosem této práce je návrh nových CMOS struktur: CCII (Current Conveyor Second Generation) na základě BD (Bulk Driven), FG (Floating Gate) a QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) na základě FG, transkonduktor na základě nové techniky BD_QFG (Bulk Driven_Quasi Floating Gate), CCCDBA (Current Controlled Current Differencing Buffered Amplifier) na základě GD (Gate Driven), VDBA (Voltage Differencing Buffered Amplifier) na základě GD a DBeTA (Differential_Input Buffered and External Transconductance Amplifier) na základě BD. Dále je uvedeno několik zajímavých aplikací užívajících výše jmenované prvky. Získané výsledky simulací odpovídají teoretickým předpokladům.The dissertation thesis deals with implementing new structures of modern active elements working in voltage_, current_, and mixed mode. The functionality and behavior of these elements have been verified by SPICE simulation. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of those elements. However, a big attention to implement active elements by utilizing LV LP (Low Voltage Low Power) techniques is given in this thesis. This attention came from the fact that growing demand of portable electronic equipments and implantable medical devices are pushing the development towards LV LP integrated circuits because of their influence on batteries lifetime. More specifically, the main contribution of this thesis is to implement new CMOS structures of: CCII (Current Conveyor Second Generation) based on BD (Bulk Driven), FG (Floating Gate) and QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) based on FG; Transconductor based on new technique of BD_QFG (Bulk Driven_Quasi Floating Gate); CCCDBA (Current Controlled Current Differencing Buffered Amplifier) based on conventional GD (Gate Driven); VDBA (Voltage Differencing Buffered Amplifier) based on GD. Moreover, defining new active element i.e. DBeTA (Differential_Input Buffered and External Transconductance Amplifier) based on BD is also one of the main contributions of this thesis. To confirm the workability and attractive properties of the proposed circuits many applications were exhibited. The given results agree well with the theoretical anticipation.

A voltage-mode PID controller using a single CFOA and only grounded capacitors

Minaei, Shahram (Dogus Author)A new voltage-mode (VM) proportional integral derivative (PID) controller employing only a single active component named Current Feedback Operational Amplifier (CFOA), two resistors and two grounded capacitors is proposed. The proposed PID controller employs a canonical number of only grounded capacitors without requiring any critical passive component matching conditions and cancellation constraints. It has high input and low output impedances; thus, it can be easily cascaded with other VM structures. It can be easily constructed by a single commercially available active element. Frequency-dependent non-ideal gain and parasitic impedance effects on the performance of the proposed PID controller are investigated. The performance of the proposed PID controller circuit is demonstrated by using PSPICE circuit simulation program and an experiment. Also, 0.18 μm CMOS TSMC technology parameters with ±2 V supply voltages are used. Total power dissipation of the proposed PID controller is 1.64 mW