244,718 research outputs found

    Memory-Aware Scheduling for Fixed Priority Hard Real-Time Computing Systems

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    As a major component of a computing system, memory has been a key performance and power consumption bottleneck in computer system design. While processor speeds have been kept rising dramatically, the overall computing performance improvement of the entire system is limited by how fast the memory can feed instructions/data to processing units (i.e. so-called memory wall problem). The increasing transistor density and surging access demands from a rapidly growing number of processing cores also significantly elevated the power consumption of the memory system. In addition, the interference of memory access from different applications and processing cores significantly degrade the computation predictability, which is essential to ensure timing specifications in real-time system design. The recent IC technologies (such as 3D-IC technology) and emerging data-intensive real-time applications (such as Virtual Reality/Augmented Reality, Artificial Intelligence, Internet of Things) further amplify these challenges. We believe that it is not simply desirable but necessary to adopt a joint CPU/Memory resource management framework to deal with these grave challenges. In this dissertation, we focus on studying how to schedule fixed-priority hard real-time tasks with memory impacts taken into considerations. We target on the fixed-priority real-time scheduling scheme since this is one of the most commonly used strategies for practical real-time applications. Specifically, we first develop an approach that takes into consideration not only the execution time variations with cache allocations but also the task period relationship, showing a significant improvement in the feasibility of the system. We further study the problem of how to guarantee timing constraints for hard real-time systems under CPU and memory thermal constraints. We first study the problem under an architecture model with a single core and its main memory individually packaged. We develop a thermal model that can capture the thermal interaction between the processor and memory, and incorporate the periodic resource sever model into our scheduling framework to guarantee both the timing and thermal constraints. We further extend our research to the multi-core architectures with processing cores and memory devices integrated into a single 3D platform. To our best knowledge, this is the first research that can guarantee hard deadline constraints for real-time tasks under temperature constraints for both processing cores and memory devices. Extensive simulation results demonstrate that our proposed scheduling can improve significantly the feasibility of hard real-time systems under thermal constraints

    A reconfigurable real-time SDRAM controller for mixed time-criticality systems

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    Verifying real-time requirements of applications is increasingly complex on modern Systems-on-Chips (SoCs). More applications are integrated into one system due to power, area and cost constraints. Resource sharing makes their timing behavior interdependent, and as a result the verification complexity increases exponentially with the number of applications. Predictable and composable virtual platforms solve this problem by enabling verification in isolation, but designing SoC resources suitable to host such platforms is challenging. This paper focuses on a reconfigurable SDRAM controller for predictable and composable virtual platforms. The main contributions are: 1) A run-time reconfigurable SDRAM controller architecture, which allows trade-offs between guaranteed bandwidth, response time and power. 2) A methodology for offering composable service to memory clients, by means of composable memory patterns. 3) A reconfigurable Time-Division Multiplexing (TDM) arbiter and an associated reconfiguration protocol. The TDM slot allocations can be changed at run time, while the predictable and composable performance guarantees offered to active memory clients are unaffected by the reconfiguration. The SDRAM controller has been implemented as a TLM-level SystemC model, and in synthesizable VHDL for use on an FPGA

    Virtual storage implementation on a microcomputer

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    Virtual storage is a hardware memory management technique which is gaining popularity amongst modern mainframe computers and top of the range minicomputers. It offers huge memory resources at lower cost in comparison to solid state memories of compatible size. The associated benefits are reduced component counts and lower power requirement. The trade off for the above mentioned advantages is an increase in the memory average access time. However this increase in the average access time does not appear to be a major handicap for many computer applications. With the widespread acceptance of microcomputer systems these days, more sophisticated and increasingly more complex programmes are being run on microcomputers. Demands are placed on the microcomputers for bigger memory recourses. Also the new generation microprocessors can now cater for an addressing space of many mega bytes. It is obvious that virtual storage technique is ideally suited for these new generation microprocessors since a large real memory implementation is impracticable and is out of question economically. This project investigated the feasibility of adapting an existing IMP-16C microcomputer system into a virtual storage system, assuming that a microcomputer system is single user orientated. Some of the virtual storage techniques were reviewed, in particular those that have been studied with a computer simulation of a virtual storage system. A working virtual storage computer system was implemented on the National Semiconductor IMP-16C microcomputer. the results of the simulation study. The design was based on A virtual memory of 256 K words of 16 bits was achieved. The cost to equip a system with an equivalent size real memory is about ten times the cost to manufacture the virtual storage controller. The average access time of the virtual storage computer system as implemented is an order higher than the conventional real memory system. Supplementary techniques and faster auxiliary storage can be employed to improve the average access time. This project demonstrated that a virtual storage controller can be coupled to an existing microprocessor to provide virtual memory storage at about one tenth the cost to provide the equivalent real memory storage. The virtual storage controller can be divided quite readily into functional blocks. Each block is suitable for chip level integration with LSI or VLSI technology. Implementing a virtual storage system around an existing microprocessor would be a much simpler task when these functional chips are available.Thesis (MESc) -- University of Adelaide, Department of Electrical Engineering, 198

    Semantic 3D Occupancy Mapping through Efficient High Order CRFs

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    Semantic 3D mapping can be used for many applications such as robot navigation and virtual interaction. In recent years, there has been great progress in semantic segmentation and geometric 3D mapping. However, it is still challenging to combine these two tasks for accurate and large-scale semantic mapping from images. In the paper, we propose an incremental and (near) real-time semantic mapping system. A 3D scrolling occupancy grid map is built to represent the world, which is memory and computationally efficient and bounded for large scale environments. We utilize the CNN segmentation as prior prediction and further optimize 3D grid labels through a novel CRF model. Superpixels are utilized to enforce smoothness and form robust P N high order potential. An efficient mean field inference is developed for the graph optimization. We evaluate our system on the KITTI dataset and improve the segmentation accuracy by 10% over existing systems.Comment: IROS 201

    Marea: An Efficient Application-Level Object Graph Swapper

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    International audienceAbstract During the execution of object-oriented applications, several millions of objects are created, used and then collected if they are not referenced. Prob- lems appear when objects are unused but cannot be garbage-collected because they are still referenced from other objects. This is an issue because those ob- jects waste primary memory and applications use more primary memory than they actually need. We claim that relying on the operating system's (OS) virtual memory is not always enough since it cannot take into account the domain and structure of applications. At the same time, applications have no easy way to parametrize nor cooperate with memory management. In this paper, we present Marea, an efficient application-level object graph swapper for object-oriented programming languages. Its main goal is to offer the programmer a novel so- lution to handle application-level memory. Developers can instruct our system to release primary memory by swapping out unused yet referenced objects to secondary memory. Our approach has been qualitatively and quantitatively val- idated. Our experiments and benchmarks on real-world applications show that Marea can reduce the memory footprint between 23% and 36%

    Towards a Performance Interference-aware Virtual Machine Placement Strategy for Supporting Soft Real-time Applications in the Cloud

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    REACTION 2014. 3rd International Workshop on Real-time and Distributed Computing in Emerging Applications. Rome, Italy. December 2nd, 2014.It is standard practice for cloud service providers (CSPs) to overbook physical system resources to maximize the resource utilization and make their business model more profitable. Resource overbooking can lead to performance interference, however, among the virtual machines (VMs) hosted on the physical resources causing performance un-predictability for soft real-time applications hosted in the VMs, which is unacceptable to these applications. Balancing these conflicting requirements needs a careful design of the placement strategies for hosting soft real-time applications such that the performance interference effects are minimized while still allowing resource overbooking. These placement decisions cannot be made offline because workloads change at run time. Moreover, satisfying the priorities of collocated VMs may require VM migrations, which require an online solution. This paper presents a machine learning-based, online placement solution to this problem where the system is trained using a publicly available trace of a large data center owned by Google. Our approach first classifies the VMs based on their historic mean CPU and memory usage, and performance features. Subsequently, it learns the best patterns of collocating the classified VMs by employing machine learning techniques. These extracted patterns are those that provide the lowest performance interference level on the specified host machines making them amenable to hosting soft real-time applications while still allowing resource overbooking.This work was supported in part by the National Science Foundation CAREER CNS 0845789 and AFOSR DDDAS FA9550-13-1-0227.Publicad

    Predictable Code and Data Paging for Real Time Systems

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    There is a need for using virtual memory in real-time ap-plications: using virtual addressing provides isolation between concurrent processes; in addition, paging allows the execution of applications whose size is larger than main memory capac-ity, which is useful in embedded systems where main memory is expensive and thus scarce. However, virtual memory is gen-erally avoided when developing real-time and embedded appli-cations due to predictability issues. In this paper we propose a predictable paging system in which the page loading and page eviction points are selected at compile-time. The contents of main memory is selected using an Integer Linear Programming (ILP) formulation. Our approach is applied to code, static data and stack regions of individual tasks. We show that the time re-quired for selecting memory contents is reasonable for all ap-plications including the largest ones, demonstrating the scala-bility of our approach. Experimental results compare our ap-proach with a previous one, based on graph coloring. It shows that quality of page allocation is generally improved, with an average improvement of 30 % over the previous approach. An-other comparison with a state-of-the-art demand-paging sys-tem shows that predictability does not come at the price of per-formance loss. 1

    Machine Learning on the Cloud for Pattern Recognition

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    Pattern recognition is a field of machine learning with applications to areas such as text recognition and computer vision. Machine learning algorithms, such as convolutional neural networks, may be trained to classify images. However, such tasks may be computationally intensive for a commercial computer for larger volumes or larger sizes of images. Cloud computing allows one to overcome the processing and memory constraints of average commercial computers, allowing computations on larger amounts of data. In this project, we developed a system for detection and tracking of moving human and vehicle objects in videos in real time or near real time. We trained various classifiers to identify objects of interest as either vehicular or human. We then compared the accuracy of different machine learning algorithms, and we compared the training runtime between a commercial computer and a virtual machine on the cloud

    Designing Android-Based Augmented Reality as an ICT Learning Media

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    Augmented Reality can be defined as a real environment in which virtual objects are added with the integration of computer technology. This technology can present interesting interactions for the user, because with this technology the user can feel virtual objects as if they actually exist in a real environment. This study will include AR technology to create learning media, so that the use of practicum time is maximized and allows students to understand and recognize computer networks. Research and application development using the Waterfall model provides a sequential or sequential software lifeflow approach starting from analysis, design, coding and testing. Testing the application using Black Box Testing and Augmented Reality Application Questionnaire for Network Devices went well. Minimum specifications of Augmented Reality Applications Network Devices with Operating System (OS) Android v6.0 Marshmallow, 2.1 GHz Deca-core Processor, 12 MP Camera, 2 GB Ram and 32 GB Memory with application specifications can run well
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