uCube: control platform for power electronics

This paper presents a versatile tool for development, control and testing of power electronics converters. In the last decade, many different expensive off-the-shelf tools for rapid prototyping and testing have been developed and commercialised by few market players. Recently, the increasing diffusion of low cost, Do It Yourself targeted development tools gained market shares previously controlled by conventional players. This trend has been driven by the fact that, despite their lower performances, many of these low cost systems are powerful enough to develop simple power electronics systems for learning and teaching purposes. This paper describes a control platform developed within the University of Nottingham, targeting at the market and application segment in between the expensive off-the-shelf control boards and the low cost emerging systems. The platform is based on the Microzed evaluation board, equipped with the Xilinx Zynq System-on-Chip. Its flexibility, features and performances will be addressed and examples of how they are being experimentally validated on different rigs will be provided

A Multi-layer Fpga Framework Supporting Autonomous Runtime Partial Reconfiguration

Partial reconfiguration is a unique capability provided by several Field Programmable Gate Array (FPGA) vendors recently, which involves altering part of the programmed design within an SRAM-based FPGA at run-time. In this dissertation, a Multilayer Runtime Reconfiguration Architecture (MRRA) is developed, evaluated, and refined for Autonomous Runtime Partial Reconfiguration of FPGA devices. Under the proposed MRRA paradigm, FPGA configurations can be manipulated at runtime using on-chip resources. Operations are partitioned into Logic, Translation, and Reconfiguration layers along with a standardized set of Application Programming Interfaces (APIs). At each level, resource details are encapsulated and managed for efficiency and portability during operation. An MRRA mapping theory is developed to link the general logic function and area allocation information to the device related physical configuration level data by using mathematical data structure and physical constraints. In certain scenarios, configuration bit stream data can be read and modified directly for fast operations, relying on the use of similar logic functions and common interconnection resources for communication. A corresponding logic control flow is also developed to make the entire process autonomous. Several prototype MRRA systems are developed on a Xilinx Virtex II Pro platform. The Virtex II Pro on-chip PowerPC core and block RAM are employed to manage control operations while multiple physical interfaces establish and supplement autonomous reconfiguration capabilities. Area, speed and power optimization techniques are developed based on the developed Xilinx prototype. Evaluations and analysis of these prototype and techniques are performed on a number of benchmark and hashing algorithm case studies. The results indicate that based on a variety of test benches, up to 70% reduction in the resource utilization, up to 50% improvement in power consumption, and up to 10 times increase in run-time performance are achieved using the developed architecture and approaches compared with Xilinx baseline reconfiguration flow. Finally, a Genetic Algorithm (GA) for a FPGA fault tolerance case study is evaluated as a ultimate high-level application running on this architecture. It demonstrated that this is a hardware and software infrastructure that enables an FPGA to dynamically reconfigure itself efficiently under the control of a soft microprocessor core that is instantiated within the FPGA fabric. Such a system contributes to the observed benefits of intelligent control, fast reconfiguration, and low overhead

Multimedia applications and network management support in Video Dialtone ATM network

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (leaves 63-64).by Dang Van Tran.M.S

Characterization and Validation of the GP-3 Experimental Radar System

The experimental GP-3 radar system was originally designed and built under contract for the Air Force Research Laboratory (AFRL). AFRL sought AFIT\u27s support in characterizing the as delivered\u27 performance of the GP-3. This research effort focused exclusively on software modifications and hardware validations related to the GP-3 post-processing mode. As modified, tested, and validated, the GP-3\u27s post-processing mode is now fully operational. The GP-3 is capable of transmitting and receiving bandlimited (3.5 MHz) waveforms at X-Band frequencies. System characterization tests included, noise performance and frequency response. System noise performance characterization permitted establishment of the receiver \u27noise floor\u27 and enabled determination of achievable SNRs (-22 dB to 44 dB for internal noise only). Frequency response characterization provided system coloration\u27 effects; an operational center frequency (4.25 MHz) and -3.0 dB bandwidth (4 MHz) were established. The GP-3\u27s operational post-processing capabilities were demonstrated for three systems: (1) a digital communication system, (2) a phase-coded, pulse compression radar, and (3) a radar employing nonlinear (range ambiguity) suppression (NLS). The GP-3 is now a viable research testbed - a highly capable system for adding an element of real-world credibility to any experimental, modeling, and simulation scenario