On-chip Monitoring: A Light-Weight Interconnection Network Approach

Current nanometer technologies are subjected to several adverse effects that seriously impact the yield and performance of integrated circuits. Such is the case of within-die parameters uncertainties, varying workload conditions, aging, temperature, etc. Monitoring, calibration and dynamic adaptation have appeared as promising solutions to these issues and many kinds of monitors have been presented recently. In this scenario, where systems with hundreds of monitors of different types have been proposed, the need for light-weight monitoring networks has become essential. In this work we present a light-weight network architecture based on digitization resource sharing of nodes that require a time-to-digital conversion. Our proposal employs a single wire interface, shared among all the nodes in the network, and quantizes the time domain to perform the access multiplexing and transmit the information. It supposes a 16% improvement in area and power consumption compared to traditional approaches

A Static Time Analysis of 1-bit to 32-page SCA architecture for Logic Test

This research proposes the Static Time Analysis  of  32  page  Single  cycle  access  (SCA)  architecture  for Logic test. The timing analysis of each and very path of Logic test are observed that is setup and hold timings are calculated.  It also eliminates the peak power consumption problem of conventional shift-based scan chains and reduces the activity during shift and capture cycles using Clock-Gating technique. This leads to more realistic circuit behavior during at-speed tests. It enables the complete test to run at much higher frequencies equal or close to the one in functional mode. It will be shown, that a lesser number of test cycles can be achieved compared to other published solutions. The test cycle per net based on a simple test pattern generator algorithm without test pattern compression is below 1 for larger designs and is independent of the design size. The structure allows an additional on-chip debugging signal visibility for each register. The method is backward compatible to full scan designs and existing test pattern generators and simulators can be used with a minor enhancement. It is shown how to combine the proposed solution with built-in self-test  (BIST)  and  massive parallel   scan   chains.   The   results   are   observed   on   Xilinx XC3s1600e-5fgg48

Electric field imaging

Thesis (Ph.D.)--Massachusetts Institute of Technology, School of Architecture and Planning, Program in Media Arts & Sciences, 1999.Includes bibliographical references (p. 213-216).The physical user interface is an increasingly significant factor limiting the effectiveness of our interactions with and through technology. This thesis introduces Electric Field Imaging, a new physical channel and inference framework for machine perception of human action. Though electric field sensing is an important sensory modality for several species of fish, it has not been seriously explored as a channel for machine perception. Technological applications of field sensing, from the Theremin to the capacitive elevator button, have been limited to simple proximity detection tasks. This thesis presents a solution to the inverse problem of inferring geometrical information about the configuration and motion of the human body from electric field measurements. It also presents simple, inexpensive hardware and signal processing techniques for making the field measurements, and several new applications of electric field sensing. The signal processing contribution includes synchronous undersampling, a narrowband, phase sensitive detection technique that is well matched to the capabilities of contemporary microcontrollers. In hardware, the primary contributions are the School of Fish, a scalable network of microcontroller-based transceive electrodes, and the LazyFish, a small footprint integrated sensing board. Connecting n School of Fish electrodes results in an array capable of making heterodyne measurements of any or all n(n - 1) off-diagonal entries in the capacitance matrix. The LazyFish uses synchronous undersampling to provide up to 8 high signal-to-noise homodyne measurements in a very small package. The inverse electrostatics portion of the thesis presents a fast, general method for extracting geometrical information about the configuration and motion of the human body from field measurements. The method is based on the Sphere Expansion, a novel fast method for generating approximate solutions to the Laplace equation. Finally, the thesis describes a variety of applications of electric field sensing, many enabled by the small footprint of the LazyFish. To demonstrate the School of Fish hardware and the Sphere Expansion inversion method, the thesis presents 3 dimensional position and orientation tracking of two hands.by Joshua Reynolds Smith.Ph.D

Architecture FPGA améliorée et flot de conception pour une reconfiguration matérielle en ligne efficace

The self-reconfiguration capabilities of modern FPGA architectures pave the way for dynamic applications able to adapt to transient events. The CAD flows of modern architectures are nowadays mature but limited by the constraints induced by the complexity of FPGA circuits. In this thesis, multiple contributions are developed to propose an FPGA architecture supporting the dynamic placement of hardware tasks. First, an intermediate representation of these tasks configuration data, independent from their final position, is presented. This representation allows to compress the task data up to 11x with regard to its conventional raw counterpart. An accompanying CAD flow, based on state-of-the-art tools, is proposed to generate relocatable tasks from a high-level description. Then, the online behavior of this mechanism is studied. Two algorithms allowing to decode and create in real-time the conventional bit-stream are described. In addition, an enhancement of the FPGA interconnection network is proposedto increase the placement flexibility of heterogeneous tasks, at the cost of a 10% increase in average of the critical path delay. Eventually, a configurable substitute to the configuration memory found in FPGAs is studied to ease their partial reconfiguration.Les capacités d'auto-reconfiguration des architectures FPGA modernes ouvrent la voie à des applications dynamiques capables d'adapter leur fonctionnement pour répondre à des évènements ponctuels. Les flots de reconfiguration des architectures commerciales sont aujourd'hui aboutis mais limités par des contraintes inhérentes à la complexité de ces circuits. Dans cette thèse, plusieurs contributions sont avancées afin de proposer une architecture FPGA reconfigurable permettant le placement dynamique de tâches matérielles. Dans un premier temps, une représentation intermédiaire des données de configuration de ces tâches, indépendante de leur positionnement final, est présentée. Cette représentation permet notamment d'atteindre des taux de compression allant jusqu'à 11x par rapport à la représentation brute d'une tâche. Un flot de conception basé sur des outils de l'état de l'art accompagne cette représentation et génère des tâches relogeables à partir d'une description haut-niveau. Ensuite, le comportement en ligne de ce mécanisme est étudié. Deux algorithmes permettant le décodage de ces tâches et la génération en temps-réel des données de configuration propres à l'architectures son décrits. Par ailleurs, une amélioration du réseau d'interconnexion d'une architecture FPGA est proposée pour accroître la flexibilité du placement de tâches hétérogènes, avec une augmentation de 10% en moyenne du délai du chemin critique. Enfin, une alternative programmable aux mémoires de configuration de ces circuits est étudiée pour faciliter leur reconfiguration partielle

Development of land based radar polarimeter processor system

The processing subsystem of a land based radar polarimeter was designed and constructed. This subsystem is labeled the remote data acquisition and distribution system (RDADS). The radar polarimeter, an experimental remote sensor, incorporates the RDADS to control all operations of the sensor. The RDADS uses industrial standard components including an 8-bit microprocessor based single board computer, analog input/output boards, a dynamic random access memory board, and power supplis. A high-speed digital electronics board was specially designed and constructed to control range-gating for the radar. A complete system of software programs was developed to operate the RDADS. The software uses a powerful real time, multi-tasking, executive package as an operating system. The hardware and software used in the RDADS are detailed. Future system improvements are recommended

A CMOS-based Hartmann-Shack Sensor for Real-Time Adaptive Optical Applications

Adaptive optical systems have a growing field of applications in opthalmology. In every adaptive system there is the need for a sensor and an actuator. The Hartmann-Shack wavefront sensor uses the displacement of spots in the focal plane of a lenslet array for subsequent calculation of the wavefront. The bandwidth of current sensors is mostly limited by software processing of the focal plane image to some tens of Hz, which makes it unsuitable for real-time adaptive optical systems. To overcome the current bandwidth limitations a fast Hartmann-Shack sensor based on an application specific integrated circuit has been developed and tested, that reaches a bandwidth of up to 6 kHz. The sensor includes photodetectors with 40% quantum efficiency at 680 nm wavelength and an image processing, that is especially suitable to reduce the effects of the common mismatching of process parameters in CMOS-based sensors (Complementary Metal Oxide Semiconductor). A special problem in ophthalmic applications is the low available spot power below 1 nW.Adaptive optical systems have a growing field of applications in opthalmology. In every adaptive system there is the need for a sensor and an actuator. The Hartmann-Shack wavefront sensor uses the displacement of spots in the focal plane of a lenslet array for subsequent calculation of the wavefront. The bandwidth of current sensors is mostly limited by software processing of the focal plane image to some tens of Hz, which makes it unsuitable for real-time adaptive optical systems. To overcome the current bandwidth limitations a fast Hartmann-Shack sensor based on an application specific integrated circuit has been developed and tested, that reaches a bandwidth of up to 6 kHz. The sensor includes photodetectors with 40% quantum efficiency at 680 nm wavelength and an image processing, that is especially suitable to reduce the effects of the common mismatching of process parameters in CMOS-based sensors (Complementary Metal Oxide Semiconductor). A special problem in ophthalmic applications is the low available spot power below 1 nW. The developed Hartmann-Shack sensor allowed wavefront measurements with an accuracy of 0.16 dpt defocus at 160 pW spot power. It has been possible for the first time, to measure wavefront aberrations at the living humane eye with 300 Hz repetition rate and to calculate the power spectral density of these aberrations

Zooplankton visualization system: design and real-time lossless image compression

In this thesis, I present a design of a small, self-contained, underwater plankton imaging system. I base the imaging system’s design on an embedded PC architecture based on PC/104-Plus standards to meet the compact size and low power requirements. I developed a simple graphical user interface to run on a real-time operating system to control the imaging system. I also address how a real-time image compression scheme implemented on an FPGA chip speeds up image transfer speeds of the imaging system. Since lossless compression of the image is required in order to retain all image details, I began with an established compression scheme like SPIHT, and latter proposed a new compression scheme that suits the imaging system’s requirements. I provide an estimate of the total amount of resources required and propose suitable FPGA chips to implement the compression scheme. Finally, I present various parallel designs by which the FPGA chip can be integrated into the imaging system

An Integrated Control and Data Acquisition System for Pharmaceutical Capsule Inspection

Pharmaphil Inc. manufactures two-part gelatin capsules for the pharmaceutical industry. Their current methods of quality control of their product is by performing manual inspection of every carton of capsules prior to shipment. In today\u27s modern manufacturing world, more efficient and cost-effective means of quality control exist. It is Pharmaphil\u27s desire to develop a custom machine vision system to replace manual inspection with a potential opportunity in the capsule manufacturing quality control market. In collaboration with the Electrical and Computer Engineering Department at the University of Windsor, a novel system was developed to achieve this goal. The objective was to develop a system capable of inspecting 1000 capsules per minute with the ability to detect holes, cracks, dents, bubble, double caps and incorrect colour or size. Using an antiquated machine vision system for capsule inspection from the mid-nineties as a base, a modern inspection system was developed that performed faster and more thorough inspections. As a measure to minimize the overall system cost as well as to increase flexibility, a full custom design was undertaken. The resulting system follows a traditional machine vision system whereby the main components include an image acquisition component, a processing unit and machine control. The designed system uses custom USB2.0 cameras to acquire images, a standard desktop PC to process image data and a custom machine control board to perform machine control and timing. The system operates with four identical quadrants operating in parallel to increase throughput. The final system developed provided a proof-of-concept for the approach taken. The machine control and image acquisition component of the system yielded a maximum throughput of 1200 capsules per minute. After incorporating image inspection, the final result was a system that was capable of inspecting capsules at a rate of about 800 capsules per minute with high accuracy. With optimizations, the system throughput can be further improved. The findings throughout the development of the prototype system provide an excellent basis from which the first generation commercial unit can be designed