700mV low power low noise implantable neural recording system design

This dissertation presents the work for design and implementation of a low power, low noise neural recording system consisting of Bandpass Amplifier and Pipelined Analog to Digital Converter (ADC) for recording neural signal activities. A low power, low noise two stage neural amplifier for use in an intelligent Radio-Frequency Identification (RFID) based on folded cascode Operational Transconductance Amplifier (OTA) is utilized to amplify the neural signals. The optimization of the number of amplifier stages is discussed to achieve the minimum power and area consumption. The amplifier power supply is 0.7V. The midband gain of amplifier is 58.4dB with a 3dB bandwidth from 0.71 to 8.26 kHz. Measured input-referred noise and total power consumption are 20.7 μVrms and 1.90 μW respectively. The measured result shows that the optimizing the number of stages can achieve lower power consumption and demonstrates the neural amplifier's suitability for instu neutral activity recording. The advantage of power consumption of Pipelined ADC over Successive Approximation Register (SAR) ADC and Delta-Sigma ADC is discussed. An 8 bit fully differential (FD) Pipeline ADC for use in a smart RFID is presented in this dissertation. The Multiplying Digital to Analog Converter (MDAC) utilizes a novel offset cancellation technique robust to device leakage to reduce the input drift voltage. Simulation results of static and dynamic performance show this low power Pipeline ADC is suitable for multi-channel neural recording applications. The performance of all proposed building blocks is verified through test chips fabricated in IBM 180nm CMOS process. Both bench-top and real animal test results demonstrate the system's capability of recording neural signals for neural spike detection

Small Form Factor Hybrid CMOS/GaN Buck Converters for 10W Point of Load Applications

abstract: Point of Load (PoL) converters are important components to the power distribution system in computer power supplies as well as automotive, space, nuclear, and medical electronics. These converters often require high output current capability, low form factor, and high conversion ratios (step-down) without sacrificing converter efficiency. This work presents hybrid silicon/gallium nitride (CMOS/GaN) power converter architectures as a solution for high-current, small form-factor PoL converters. The presented topologies use discrete GaN power devices and CMOS integrated drivers and controller loop. The presented power converters operate in the tens of MHz range to reduce the form factor by reducing the size of the off-chip passive inductor and capacitor. Higher conversion ratio is achieved through a fast control loop and the use of GaN power devices that exhibit low parasitic gate capacitance and minimize pulse swallowing. This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor. Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Low-voltage Low-power Bulk-driven CMOS Op-Amp Using Negative Miller Compensation for ECG

Two bulk-driven CMOS (Complementary Metal Oxide Semiconductor) operational amplifier (op-amp) designs for electrocardiogram (ECG) application are presented and compared in this paper. Both op-amps are based on two-stage amplification, where bulk-driven differential input is the first stage, while additional DC gain is the second stage. Different compensation techniques were integrated in each op-amp design. Standard Miller compensation was used for the first op-amp parallel with the second stage. The novelty of the second op-amp is that it utilizes negative Miller compensation between the bulk-driven input node and the output node of the first stag, while standard Miller compensation was used in the second stage. The purpose of this work was to compare DC gain, phase margin (PM) and unit gain frequency (UGF) obtained through different simulated compensation strategies and test results. The op-amps were simulated using 0.25 μm CMOS technology. The simulation results are presented using the standard model libraries from Tanner EDA tools, operating on a single rail +0.8V power supply

Design of a 20MHz Transimpedance Low-pass Filter with an Adapted 3rd Order Inverse Chebyshev Response

In Multi-Standard receivers, multiple radios co-exist in close proximity. A desired signal can be accompanied by significantly stronger out-of band interferers or blockers, which can severely degrade a receiver's sensitivity through gain compression of the blocks in the receiver chain. This work presents a new Transimpedance Amplifier (TIA) low-pass filter architecture which seeks to solve the out-of-band blocker problem of the existing architectures. A higher order filtering is embedded within the TIA in the form of an active feedback to provide more attenuation to out-of-band blockers. The active feedback circuitry feeds back an equivalent amount of current to the input node to cancel out incoming out-of-band blockers while maintaining an acceptable voltage swing at the output of the TIA. The proposed TIA filter has a channel bandwidth of 20MHz, and can processes interferers of +/- 10mA fully differential without saturating the opamps. The maximum single ended voltage swing at all the nodes is +/- 200mV. All the circuits were designed in IBM 180nm CMOS process with a supply voltage of 1.8V

Low-voltage Low-power Bulk-driven CMOS Op-Amp Using Negative Miller Compensation for ECG

Two bulk-driven CMOS (Complementary Metal Oxide Semiconductor) operational amplifier (op-amp) designs for electrocardiogram (ECG) application are presented and compared in this paper. Both op-amps are based on two-stage amplification, where bulk-driven differential input is the first stage, while additional DC gain is the second stage. Different compensation techniques were integrated in each op-amp design. Standard Miller compensation was used for the first op-amp parallel with the second stage. The novelty of the second op-amp is that it utilizes negative Miller compensation between the bulk-driven input node and the output node of the first stag, while standard Miller compensation was used in the second stage. The purpose of this work was to compare DC gain, phase margin (PM) and unit gain frequency (UGF) obtained through different simulated compensation strategies and test results. The op-amps were simulated using 0.25 μm CMOS technology. The simulation results are presented using the standard model libraries from Tanner EDA tools, operating on a single rail +0.8V power supply

Super-Gain-Boosted AB-AB Fully Differential Miller Op-Amp With 156dB Open-Loop Gain and 174MV/V MHZ pF/µW Figure of Merit in 130nm CMOS Technology

Article number 9400400A fully differential Miller op-amp with a composite input stage using resistive local common-mode feedback and regulated cascode transistors is presented here. High gain pseudo-differential auxiliary amplifiers are used to implement the regulated cascode transistors in order to boost the output impedance of the composite input stage and the open-loop gain of the op-amp. Both input and output stages operate in class AB mode. The proposed op-amp has been simulated in a 130nm commercial CMOS process technology. It operates from a 1.2V supply and has a close to rail-to-rail differential output swing. It has 156dB DC open-loop gain and 63MHz gain-bandwidth product with a 30pF capacitive load. The op-amp has a DC open-loop gain figure of merit FOMAOLDC of 174 (MV/V) MHz pF/µW and large-signal figure of merit FOMLS of 3(V/µs) pF/µW.Consejería de Economía y Conocimiento of Junta de Andalucía P18-FR-4317Consejo Nacional de Ciencia y Tecnología (España) A1-S-43214Agencia Estatal de Investigación TEC2016-80396-C

Super-gain-boosted AB-AB fully differential Miller op-amp with 156dB open-loop gain and 174MV/V MHZ pF/uW figure of merit in 130nm CMOS technology

A fully differential Miller op-amp with a composite input stage using resistive local common-mode feedback and regulated cascode transistors is presented here. High gain pseudo-differential auxiliary amplifiers are used to implement the regulated cascode transistors in order to boost the output impedance of the composite input stage and the open-loop gain of the op-amp. Both input and output stages operate in class AB mode. The proposed op-amp has been simulated in a 130nm commercial CMOS process technology. It operates from a 1.2V supply and has a close to rail-to-rail differential output swing. It has 156dB DC open-loop gain and 63MHz gain-bandwidth product with a 30pF capacitive load. The op-amp has a DC open-loop gain figure of merit FOMAOLDC of 174 (MV/V) MHz pF/uW and large-signal figure of merit FOMLS of 3(V/us) pF/uW.This work was supported in part by the Spanish Government Agencia Estatal de Investigación (AEI) under Grant TEC2016-80396-C2, in part by the Consejería de Economía y Conocimiento of Junta de Andalucía under Grant P18-FR-4317 (both projects received support from the Fondo Europeo de Desarrollo Regional (FEDER)), and in part by the Consejo Nacional de Ciencia y Tecnologia (CONACyT) under Grant A1-S-43214

New mathematical formulation for designing a fully differential self-biased folded cascode amplifier

One of the most important building blocks in analog circuit design is the operational amplifiers. This is because of their versatility and wide spread usage in many applications such as communications transmitters and receivers, analog to digital converters, or any other application that requires a small signal to be amplified. The basic amplifier topologies are introduced. Then, some operational amplifiers topologies are introduced with some techniques to self bias these amplifiers. The folded cascode fully differential Op-Amp with self bias is presented. This is one of the newest amplifier topologies which provide stable self-biased amplifiers. A new mathematical model for fully differential folded cascode amplifiers is presented and generalized to include the family of fully differential complementary amplifiers. This formulation focuses on deriving detailed design equations for the amplifier gain and frequency response. The equations are verified through time domain and frequency domain simulations of different fabrication processes to ensure the validity of the model across a wide range of processes. The model was verified against TMSC 180nm, 250nm, and 350nm fabrication processes. The new model agrees well with simulations; with 1% error for the amplifier gain and \u3c7% error for amplifier bandwidth. The relatively high error value for the bandwidth is because the model considers the worst case scenario and overestimates the output capacitance. Finally, the algorithm of getting this formulation is extended to include special and commonly used cases. This formulation proved to be very useful in designing stable, self-biased, fully differential folded cascode amplifiers

Design of a Comparator and an Amplifier in CMOS using standard logic gates

Using standard logic gates in CMOS, or standard-cells, has the advantage of full synthe- sizability, as well as the voltage scalability between technologies. In this work a general pur- pose standard-cell-based voltage comparator and amplifier are presented. The objective is to design a general purpose standard-cell-based comparator and ampli- fier in 130 nm CMOS by optimizing the already existing topologies with the aim of improving some of the specifications of the studied topologies. Various simulation testbenches were made to test the studied topologies of comparators and amplifiers, in which the results were compared. The top performing standard-cell com- parator and amplifier were then modified. After successfully designing the comparator, it was used in the design of an opamp-less Sigma-Delta modulator (ΣΔM). The proposed comparator is an OR-AND-Inverter-based comparator with dual inputs and outputs, achieving a delay of 109 ps, static input offset of 591 μV, and random offset of 10.42 μV, while dissipating 890 μW, when clocked at 1.5 GHz. The proposed amplifier is a single-path three-stage inverter-based operational transcon- ductance amplifier (OTA) with active common-mode feedback loop, achieving a DC gain of 63 dB, 1444 MHz of unity-gain bandwidth, 51º of phase margin while dissipating 1098 μW, considering a load of 1 pF. The proposed comparator was employed in the ΣΔM with a standard-cell based edge- triggered flip-flop. The ΣΔM, with a sampling frequency of 2 MHz and a signal bandwidth of 2.5 kHz, achieved a peak SNDR of 69 dB while dissipating only 136.7 μW.Utilizando portas lógicas básicas em CMOS oferece a vantagem de um circuito comple- tamente sintetizável, tal como o escalamento de tensão entre tecnologias. Neste trabalho são apresentados um comparador de tensão e um amplificador utilizando portas lógicas. O objetivo deste trabalho é desenhar um comparador e um amplificador utilizando por- tas lógicas através do estudo e otimização de topologias já existentes com a finalidade de me- lhoramento de algumas das especificações das mesmas. Foram realizados vários bancos de teste para testar as topologias estudadas de compa- radores e amplificadores, em que os resultados foram comparados. As topologias de compa- radores e amplificadores de portas lógicas com melhor performance foram então modificadas. Após o comparador ter sido projetado com sucesso, foi utilizado na projeção de um modula- dor Sigma-Delta (ΣΔM) opamp-less. O comparador proposto é um OR-AND-Inversor com duas entradas e saídas, que apre- senta um atraso de 109 ps, offset estático na entrada de 591 μV, offset aleatório de 10.42 μV, enquanto dissipando 890 μW, utilizando uma frequência de relógio de 1.5 GHz O amplificador proposto é um amplificador operacional de transcondutância single- path three-stage inverter-based com um loop ativo de realimentação do modo-comum, que apresenta um ganho DC de 63 dB, 1444 MHz de ganho-unitário de largura de banda, 51º de margem de fase e dissipando 1098 μW, considerando uma carga de 1 pF. O comparador proposto foi aplicado no ΣΔM com um flip-flop edge-triggered baseado em portas lógicas. O ΣΔM, com uma frequência de amostragem de 2 MHz e uma largura de banda de 2.5 kHz, apresentou um SNDR máximo de 69 dB enquanto dissipando apenas 136.7 μW