Automating question generation from educational text

The use of question-based activities (QBAs) is wide-spread in education, traditionally forming an integral part of the learning and assessment process. In this paper, we design and evaluate an automated question generation tool for formative and summative assessment in schools. We present an expert survey of one hundred and four teachers, demonstrating the need for automated generation of QBAs, as a tool that can significantly reduce the workload of teachers and facilitate personalized learning experiences. Leveraging the recent advancements in generative AI, we then present a modular framework employing transformer based language models for automatic generation of multiple-choice questions (MCQs) from textual content. The presented solution, with distinct modules for question generation, correct answer prediction, and distractor formulation, enables us to evaluate different language models and generation techniques. Finally, we perform an extensive quantitative and qualitative evaluation, demonstrating trade-offs in the use of different techniques and models.Comment: Accepted to AI-2023 (Forty-third SGAI International Conference on Artificial Intelligence) as a long paper, link: http://www.bcs-sgai.org/ai202

Hybrid automated reliability predictor integrated work station (HiREL)

The Hybrid Automated Reliability Predictor (HARP) integrated reliability (HiREL) workstation tool system marks another step toward the goal of producing a totally integrated computer aided design (CAD) workstation design capability. Since a reliability engineer must generally graphically represent a reliability model before he can solve it, the use of a graphical input description language increases productivity and decreases the incidence of error. The captured image displayed on a cathode ray tube (CRT) screen serves as a documented copy of the model and provides the data for automatic input to the HARP reliability model solver. The introduction of dependency gates to a fault tree notation allows the modeling of very large fault tolerant system models using a concise and visually recognizable and familiar graphical language. In addition to aiding in the validation of the reliability model, the concise graphical representation presents company management, regulatory agencies, and company customers a means of expressing a complex model that is readily understandable. The graphical postprocessor computer program HARPO (HARP Output) makes it possible for reliability engineers to quickly analyze huge amounts of reliability/availability data to observe trends due to exploratory design changes

MDA-based ATL transformation to generate MVC 2 web models

Development and maintenance of Web application is still a complex and error-prone process. We need integrated techniques and tool support for automated generation of Web systems and a ready prescription for easy maintenance. The MDA approach proposes an architecture taking into account the development and maintenance of large and complex software. In this paper, we apply MDA approach for generating PSM from UML design to MVC 2Web implementation. That is why we have developed two meta-models handling UML class diagrams and MVC 2 Web applications, then we have to set up transformation rules. These last are expressed in ATL language. To specify the transformation rules (especially CRUD methods) we used a UML profiles. To clearly illustrate the result generated by this transformation, we converted the XMI file generated in an EMF (Eclipse Modeling Framework) model.Comment: International Journal of Computer Science & Information Technology-201

A Generic Technique for Domain-Specific Visual Language Model Refactoring to Patterns

As the popularity of domain-specific visual languages (DSVLs) grows, concerns have arisen regarding quality assurance and evolvability of their meta-models and model instances. In this paper we address aspects of automated DSVL model instance modification for quality improvement based on refactoring specifications. We propose a graph transformation-based visual language approach for DSVL authors to specify the matching and discovery of DSVL “bad model smells” and the application of pattern-based solutions in a DSVL meta-tool. As an outcome, DSVL users are provided with pattern-based design evolution support as refactorings for their DSVL-based domain models

Formal Modelling, Testing and Verification of HSA Memory Models using Event-B

The HSA Foundation has produced the HSA Platform System Architecture Specification that goes a long way towards addressing the need for a clear and consistent method for specifying weakly consistent memory. HSA is specified in a natural language which makes it open to multiple ambiguous interpretations and could render bugs in implementations of it in hardware and software. In this paper we present a formal model of HSA which can be used in the development and verification of both concurrent software applications as well as in the development and verification of the HSA-compliant platform itself. We use the Event-B language to build a provably correct hierarchy of models from the most abstract to a detailed refinement of HSA close to implementation level. Our memory models are general in that they represent an arbitrary number of masters, programs and instruction interleavings. We reason about such general models using refinements. Using Rodin tool we are able to model and verify an entire hierarchy of models using proofs to establish that each refinement is correct. We define an automated validation method that allows us to test baseline compliance of the model against a suite of published HSA litmus tests. Once we complete model validation we develop a coverage driven method to extract a richer set of tests from the Event-B model and a user specified coverage model. These tests are used for extensive regression testing of hardware and software systems. Our method of refinement based formal modelling, baseline compliance testing of the model and coverage driven test extraction using the single language of Event-B is a new way to address a key challenge facing the design and verification of multi-core systems.Comment: 9 pages, 10 figure

CRISTAL: Collection of Resource-Centric Supporting Tools and Languages

In this demo, we introduce CRISTAL (Collection of ResourcecentrIc Supporting Tools and Languages), a tool suite aimed at improving the human resource management capabilities of current Business Process Management Systems (BPMSs), covering the design and enactment phases of the business process (BP) life cycle. The central element is Resource Assignment Language (RAL), a Domain Specific Language (DSL) for specifying resource assignments in process models. RAL’s strong analysis capabilities enable the automated resolution of resource assignment expressions both (i) at design time, serving for post-design analysis to find and correct potential problems prior to execution, and (ii) at run time, in order to execute the BP in an existing BPMS considering the RAL assignments for resource allocation. The resource assignments can be directly modelled in a Business Process Modelling Notation (BPMN) diagram, or specified by means of a RACI matrix. in the latter case, CRISTAL can take all the RACI information automatically and introduce it into a resource-unaware BPMN model at any moment, resulting in a RACI-aware BP model (and, thus, a resource-aware BP model)

Comparison of different design alternatives for hardware-in-the-loop of power converters

This paper aims to compare different design alternatives of hardware-in-the-loop (HIL) for emulating power converters in Field Programmable Gate Arrays (FPGAs). It proposes various numerical formats (fixed and floating-point) and different approaches (pure VHSIC Hardware Description Language (VHDL), Intellectual Properties (IPs), automated MATLAB HDL code, and High-Level Synthesis (HLS)) to design power converters. Although the proposed models are simple power electronics HIL systems, the idea can be extended to any HIL system. This study compares the design effort of different coding methods and numerical formats considering possible synthesis tools (Precision and Vivado), and it comprises an analytical discussion in terms of area and speed. The different models are synthesized as ad-hoc modules in general-purpose FPGAs, but also using the NI myRIO device as an example of a commercial tool capable of implementing HIL models. The comparison confirms that the optimum design alternative must be chosen based on the application (complexity, frequency, etc.) and designers’ constraints, such as available area, coding expertise, and design effor