Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Processing circuit with asymmetry corrector and convolutional encoder for digital data

A processing circuit is provided for correcting for input parameter variations, such as data and clock signal symmetry, phase offset and jitter, noise and signal amplitude, in incoming data signals. An asymmetry corrector circuit performs the correcting function and furnishes the corrected data signals to a convolutional encoder circuit. The corrector circuit further forms a regenerated clock signal from clock pulses in the incoming data signals and another clock signal at a multiple of the incoming clock signal. These clock signals are furnished to the encoder circuit so that encoded data may be furnished to a modulator at a high data rate for transmission

Automatic oscillator frequency control system

A frequency control system makes an initial correction of the frequency of its own timing circuit after comparison against a frequency of known accuracy and then sequentially checks and corrects the frequencies of several voltage controlled local oscillator circuits. The timing circuit initiates the machine cycles of a central processing unit which applies a frequency index to an input register in a modulo-sum frequency divider stage and enables a multiplexer to clock an accumulator register in the divider stage with a cyclical signal derived from the oscillator circuit being checked. Upon expiration of the interval, the processing unit compares the remainder held as the contents of the accumulator against a stored zero error constant and applies an appropriate correction word to a correction stage to shift the frequency of the oscillator being checked. A signal from the accumulator register may be used to drive a phase plane ROM and, with periodic shifts in the applied frequency index, to provide frequency shift keying of the resultant output signal. Interposition of a phase adder between the accumulator register and phase plane ROM permits phase shift keying of the output signal by periodic variation in the value of a phase index applied to one input of the phase adder

Software Defined DCF77 Receiver

This paper shows the solution of time stamp software defined receiver integration into low cost com-mercial devices. The receiver is based on a general pur-pose processor and its analog to digital converter. The amplified signal from a narrow-band antenna is connected to the converter and no complicated filtration has to be used. All signal processing is digitally provided by the processor. During signal reception, the processor stays available for its main tasks and signal processing con-sumes only a small part of its computational power

Programmable rate modem utilizing digital signal processing techniques

The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery

半導体光増幅器を用いた光デジタル・アナログ相互変換

　デジタル・アナログ変換(D/A変換)とアナログ・デジタル変換(A/D変換)は，電子デバイスや光学システム内でデジタル信号とアナログ信号を接続するための重要な機能であり，通信ネットワークを含む幅広い分野で利用されている．近年，デジタル信号処理技術の発達に伴い，より高性能なD/A変換器やA/D変換器の需要が高まっている．しかし，電気的なD/A変換器やA/D変換器は，ジッタ制限，電磁干渉，RC遅延などの高速動作における固有のボトルネックを有している．よって，コストや複雑さを犠牲とし，1つのシステムに複数の電気的なD/A変換器やA/D変換器を様々な手法で統合し，高速な変換を実現している．一方，光信号処理は電気信号処理の限界を克服できるため，光D/A変換器や光A/D変換器の実現が注目されている．主に特殊な光ファイバ内で発生する非線形光学効果を用いた光D/A変換器や光A/D変換器が報告されているが，構成が複雑であり，高いパワーが必要といった課題がある．　半導体光増幅器(SOA)は，小型かつ低消費電力であり，高い非線形性を有していることから，波長変換などの光信号処理デバイスとしても利用されている．SOAを用いた光D/A変換や光A/D変換は，相互利得変調を用いた手法がそれぞれ1件ずつ報告されており，2 bitの変換を実証しているが，高分解能化には多数のSOAが必要となる等の課題が存在する．　周波数チャープは，SOAで発生する特異な現象であり，デバイスの屈折率変化に基づいて周波数変動を誘導する．これまでに，SOAのチャープ特性が，長波長側への周波数シフトであるレッドチャープと短波長側への周波数シフトであるブルーチャープが異なる特性を有することを示されている．このレッドチャープを活用した光A/D変換器が提案されており，構成な構成かつ低入力パワーで8レベルの光量子化に成功している．　本論文では，SOAのブルーチャープを用いた光D/A変換の検討を行い，2 bitの光D/A変換を実証した．そして，その変換性能を微分非線形性(DNL)，積分非線形性(INL)，有効ビット数(ENOB)を用いて評価した．さらに，ブルーチャープを用いた光D/A変換とレッドチャープを用いた光A/D変換を組み合わせた，2 bitの光デジタル・アナログ相互変換を実証した．周波数チャープを用いた光D/A変換と光A/D変換は，単一のSOAを用いた簡素な構成とモノリシック集積の可能性を有している．得られた結果は，アナログ信号とデジタル信号を光領域で相互接続する手法として，提案方式の有用性を示した．電気通信大学201

Digital demodulator-correlator

An apparatus for demodulation and correlation of a code modulated 10 MHz signal is presented. The apparatus is comprised of a sample and hold analog-to-digital converter synchronized by a frequency coherent 40 MHz pulse to obtain four evenly spaced samples of each of the signal. Each sample is added or subtracted to or from one of four accumulators to or from the separate sums. The correlation functions are then computed. As a further feature of the invention, multipliers are each multiplied by a squarewave chopper signal having a period that is long relative to the period of the received signal to foreclose contamination of the received signal by leakage from either of the other two terms of the multipliers