109 research outputs found

    Customized Integrated Circuits for Scientific and Medical Applications

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    Energy Efficient Techniques For Algorithmic Analog-To-Digital Converters

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    Analog-to-digital converters (ADCs) are key design blocks in state-of-art image, capacitive, and biomedical sensing applications. In these sensing applications, algorithmic ADCs are the preferred choice due to their high resolution and low area advantages. Algorithmic ADCs are based on the same operating principle as that of pipelined ADCs. Unlike pipelined ADCs where the residue is transferred to the next stage, an N-bit algorithmic ADC utilizes the same hardware N-times for each bit of resolution. Due to the cyclic nature of algorithmic ADCs, many of the low power techniques applicable to pipelined ADCs cannot be directly applied to algorithmic ADCs. Consequently, compared to those of pipelined ADCs, the traditional implementations of algorithmic ADCs are power inefficient. This thesis presents two novel energy efficient techniques for algorithmic ADCs. The first technique modifies the capacitors' arrangement of a conventional flip-around configuration and amplifier sharing technique, resulting in a low power and low area design solution. The other technique is based on the unit multiplying-digital-to-analog-converter approach. The proposed approach exploits the power saving advantages of capacitor-shared technique and capacitor-scaled technique. It is shown that, compared to conventional techniques, the proposed techniques reduce the power consumption of algorithmic ADCs by more than 85\%. To verify the effectiveness of such approaches, two prototype chips, a 10-bit 5 MS/s and a 12-bit 10 MS/s ADCs, are implemented in a 130-nm CMOS process. Detailed design considerations are discussed as well as the simulation and measurement results. According to the simulation results, both designs achieve figures-of-merit of approximately 60 fJ/step, making them some of the most power efficient ADCs to date

    Energy Efficient Techniques For Algorithmic Analog-To-Digital Converters

    Get PDF
    Analog-to-digital converters (ADCs) are key design blocks in state-of-art image, capacitive, and biomedical sensing applications. In these sensing applications, algorithmic ADCs are the preferred choice due to their high resolution and low area advantages. Algorithmic ADCs are based on the same operating principle as that of pipelined ADCs. Unlike pipelined ADCs where the residue is transferred to the next stage, an N-bit algorithmic ADC utilizes the same hardware N-times for each bit of resolution. Due to the cyclic nature of algorithmic ADCs, many of the low power techniques applicable to pipelined ADCs cannot be directly applied to algorithmic ADCs. Consequently, compared to those of pipelined ADCs, the traditional implementations of algorithmic ADCs are power inefficient. This thesis presents two novel energy efficient techniques for algorithmic ADCs. The first technique modifies the capacitors' arrangement of a conventional flip-around configuration and amplifier sharing technique, resulting in a low power and low area design solution. The other technique is based on the unit multiplying-digital-to-analog-converter approach. The proposed approach exploits the power saving advantages of capacitor-shared technique and capacitor-scaled technique. It is shown that, compared to conventional techniques, the proposed techniques reduce the power consumption of algorithmic ADCs by more than 85\%. To verify the effectiveness of such approaches, two prototype chips, a 10-bit 5 MS/s and a 12-bit 10 MS/s ADCs, are implemented in a 130-nm CMOS process. Detailed design considerations are discussed as well as the simulation and measurement results. According to the simulation results, both designs achieve figures-of-merit of approximately 60 fJ/step, making them some of the most power efficient ADCs to date

    Wide-Dynamic Range Image Sensor Prototype Based On Digital Readout Integrated Circuit

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    Emerging infrared and visible imaging applications require higher sensitivity, larger pixel array, larger contrast ratio (dynamic range), very low power consumption and faster data readout rate operations all at the same time. Some of these applications are camera surveillance used both in day/night (very bright and dark conditions), medical diagnostics, weather forecasting, and aerial search & rescue operations etc. The digital-pixel focal plane array (DFPA) implemented in this thesis has the capabilities to capture a wide dynamic range of more than 120dB in a single global shutter without saturating the pixels at a huge frame rate of more than 500Hz. An adaptive Integration Window technique has been developed which ensures that we are able to measure such a huge dynamic range using a counter of only 10 bits (this helps us lower the power consumption of the design). This proposed image sensor has been designed, fabricated and tested in 65nm CMOS technology. It has 16 x 16-pixel array with 16 x 9 pixels with an inbuilt Silicon APD for optical testing and 16 x 7 dummy pixels for electrical testing. Our design proposes an off-chip digital calibration technique to cut down the burden on the analog circuitry. The sensor design achieved more than 128dB+ of dynamic range with a DNL/INL of 0.65/1.65 respectively with a power consumption of only 0.58 uW/pixel. The digital calibration scheme successfully cuts down the pixel-pixel variation standard deviations by a factor of 4. The proposed image sensor design should be able to address most of the short-comings of conventional FPAs and provides a one-shot solution to the design of high performance CMOS image sensors

    Linear CCD-Based Spectrometry Using Either an ASIC or FPGA Design Methodology

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    At room temperature, high-responsivity charge-coupled devices (CCD) comprising arrays of several thousand linear photodiodes are readily available. These sensors are capable of ultraviolet to near infrared wavelengths sensing with detecting resolutions of up to 24 dots per millimeter. Their applicability in novel spectrometry applications has been demonstrated. However, the complexity of their timing, image acquisition, and processing necessitates sophisticated peripheral circuitry for viable output. In this chapter, we outline the application specifications for a versatile spectrometer that is reliant on a field programmable gate array (FPGA) automation. The sustained throughput is 1.23 gigabit per second 8-bit color readout rate. This approach is attractive because the final FPGA design may be reconfigured readily to a single, branded, application-specific integrated circuit (ASIC) to drive a wider range of linear CCDs on the market. This is advantageous for rapid development and deployment of the spectrometer instrument

    Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor

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    Due to the switch from CCD to CMOS technology, CMOS based image sensors have become smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart from the extensive set of applications requiring image sensors, the next technological breakthrough in imaging would be to consolidate and completely shift the conventional CMOS image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative technology in the imaging field, allowing multiple silicon tiers with different functions to be stacked on top of each other. The technology allows for an extreme parallelism of the pixel readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked image sensor, and the parallelism of the readout can remain constant at any spatial resolution of the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor array resolution. The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked image sensors, structured with parallel readout circuitries. The readout circuit’s key requirements are low noise, speed, low-area (for higher parallelism), and low power. A CMOS imaging review is presented through a short historical background, followed by the description of the motivation, the research goals, and the work contributions. The fundamentals of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features, the essential building blocks, types of operation, as well as their physical characteristics and their evaluation metrics. Following up on this, the document pays attention to the readout circuit’s noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron noise imagers. Lastly, the fabricated test CIS device performances are reported along with conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future work. A part of the developed research work is located in the Appendices.Devido Ă  mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais rĂĄpidos, e mais recentemente, ultrapassaram os sensores CCD no que respeita Ă  qualidade de imagem. Para alĂ©m do vasto conjunto de aplicaçÔes que requerem sensores de imagem, o prĂłximo salto tecnolĂłgico no ramo dos sensores de imagem Ă© o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a tecnologia “3D-stacked”. O empilhamento de chips Ă© relativamente recente e Ă© uma tecnologia inovadora no campo dos sensores de imagem, permitindo vĂĄrios planos de silĂ­cio com diferentes funçÔes poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um paralelismo extremo na leitura dos sinais vindos da matriz de pĂ­xeis. AlĂ©m disso, num sensor de imagem de planos de silĂ­cio empilhados, os circuitos de leitura estĂŁo posicionados debaixo da matriz de pĂ­xeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer resolução espacial, permitindo assim atingir um extremo baixo ruĂ­do e um alto debito de imagens, virtualmente para qualquer resolução desejada. O objetivo deste trabalho Ă© o de desenhar circuitos de leitura de coluna de muito baixo ruĂ­do, planeados para serem empregues em sensores de imagem “3D-stacked” com estruturas altamente paralelizadas. Os requisitos chave para os circuitos de leitura sĂŁo de baixo ruĂ­do, rapidez e pouca ĂĄrea utilizada, de forma a obter-se o melhor rĂĄcio. Uma breve revisĂŁo histĂłrica dos sensores de imagem CMOS Ă© apresentada, seguida da motivação, dos objetivos e das contribuiçÔes feitas. Os fundamentos dos sensores de imagem CMOS sĂŁo tambĂ©m abordados para expor as suas caracterĂ­sticas, os blocos essenciais, os tipos de operação, assim como as suas caracterĂ­sticas fĂ­sicas e suas mĂ©tricas de avaliação. No seguimento disto, especial atenção Ă© dada Ă  teoria subjacente ao ruĂ­do inerente dos circuitos de leitura e dos conversores de coluna, servindo para identificar os possĂ­veis aspetos que dificultem atingir a tĂŁo desejada performance de muito baixo ruĂ­do. Por fim, os resultados experimentais do sensor desenvolvido sĂŁo apresentados junto com possĂ­veis conjeturas e respetivas conclusĂ”es, terminando o documento com o assunto de empilhamento vertical de camadas de silĂ­cio, junto com o possĂ­vel trabalho futuro

    Time interleaved counter analog to digital converters

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    The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13ÎŒm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration

    Single Photon Counting Performance and Noise Analysis of CMOS SPAD-based Image Sensors

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    SPAD-based solid state CMOS image sensors utilising analogue integrators have attained deep sub-electron read noise (DSERN) permitting single photon counting (SPC) imaging. A new method is proposed to determine the read noise in DSERN image sensors by evaluating the peak separation and width (PSW) of single photon peaks in a photon counting histogram (PCH). The technique is used to identify and analyse cumulative noise in analogue integrating SPC SPAD-based pixels. The DSERN of our SPAD image sensor is exploited to confirm recent multi-photon threshold quanta image sensor (QIS) theory. Finally, various single and multiple photon spatio-temporal oversampling techniques are reviewed

    Design, Implementation and Evaluation of Hardware Vision Systems Dedicated to Real-Time Face Recognition

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    Human face recognition is an active area of research spanning several disciplines such as image processing, pattern recognition, and computer vision. Most researches have concentrated on the algorithms of segmentation, feature extraction, and recognition of human faces, which are generally realized by software implementation on standard computers. However, many applications of human face recognition such as human-computer interfaces, model-based video coding, and security control (Kobayashi, 2001, Yeh & Lee, 1999) need to be high-speed and real-time, for example, passing through customs quickly while ensuring security. For the last years, our laboratory has focused on face processing and obtained interesting results concerning face tracking and recognition by implementing original dedicated hardware systems. Our aim is to implement on embedded systems efficient models of unconstrained face tracking and identity verification in arbitrary scenes. The main goal of these various systems is to provide efficient robustness algorithms that only require moderated computation in order 1) to obtain high success rates of face tracking and identity verification and 2) to cope with the drastic real-time constraints. The goal of this chapter is to describe three different hardware platforms dedicated to face recognition. Each of them has been designed, implemented and evaluated in our laboratory
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