Designing HMO, an Integrated Hardware Microcode Optimizer

This Paper Discusses an Algorithm for Optimizing the Density and Parallelism of Micro coded Routines in Micro programmable Machines. Besides the Algorithm itself, the Algorithm\u27s Uses, Design Integration Problems, Architectural Requirements, and Adaptability to Conventional Machine Characteristics Are Also Discussed and Analyzed. Even Though the Paper Proposes a Hardware Implementation of the Algorithm, the Algorithm is Viewed as an Integral Part of the Entire Microcode Generation and Usage Process, from Initial High-Level Input into a Software Microcode Compiler Down to Machine-Level Execution of the Resultant Microcode on the Host Machine. It is Believed that, by Removing Much of the Traditionally Time-Consuming and Machine-Dependent Microcode Optimization from the Software Portion of This Process, the Algorithm Can Improve the overall Process

Towards a design of HMO, an integrated hardware microcode optimizer

This paper discusses an algorithm for optimizing the density and parallelism of microcoded routines in micro-programmable machines. Besides presenting the algorithm itself, this research also analyzes the algorithm\u27s uses, design integration problems, architectural requirements, and adaptability to conventional machine characteristics. Even though the paper proposes a hardware implementation of the algorithm, the algorithm is viewed as an integral part of the entire microcode generation and usage process, from initial high-level input into a software microcode compiler down to machine-level execution of the resultant microcode on the host machine. It is believed that, by removing much of the traditionally time-consuming and machine-dependent microcode optimization from the software portion of this process, the algorithm can improve the overall process --Abstract, page ii

Specifications and programs for computer software validation

Three software products developed during the study are reported and include: (1) FORTRAN Automatic Code Evaluation System, (2) the Specification Language System, and (3) the Array Index Validation System

Graphical microcode simulator with a reconfigurable datapath

Microcode is a symbolic way to simplify control design that allows changing, testing and updating the control unit of processors. By changing the microcode, the same datapath can be used for an entirely different application, such as supporting a completely different instruction set. For these reasons, a majority of control units in modern day processors are microcoded. The object was to investigate and implement a graphical microcode simulator with a reconfigurable datapath and microcode format. By allowing a wide configuration of the datapath, many types of logical processors can be designed and simulated. The resulting implemented simulator is able to fill the void in microprogramming tools since there are no graphical microcode simulators that allow such customization of the datapath. The customization of the datapath goes beyond allowing different files specifying the datapath, it allows the datapath to be created and modified using the graphical interface.This tool is able to be used to design and simulate general-purpose processors and application specific processors through datapath and microcode configurations. In the academic setting, this tool provides easier microcode testing through verification on the instruction level for instructors and provide simulation debugging through code tracing and breakpoints for students

Multiprocessor/Multicomputer Systems and Optimal Loading Techniques

This report reviews the subject of multiprocessor/multicomputer systems and optimal loading techniques. This report covers: 1. The interrelationship of Multiprocessor/Multicomputer (Multiple Instruction Stream Multiple Data Stream, MIMD) systems and other architectures by presenting a categorization of computer architectures. 2. Comparison of Multiprocessor/Multicomputer (MIMD), versus Parallel Processor (Single Instruction stream Multiple Data stream, SIMD) systems. 3. Multiprocessor/Multicomputer problems, pitfalls and new goals. 4. Investigation of loading techniques by reviewing particular MIMD executive designs

Survey on Combinatorial Register Allocation and Instruction Scheduling

Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering instructions to increase instruction-level parallelism) are essential tasks for generating efficient assembly code in a compiler. In the last three decades, combinatorial optimization has emerged as an alternative to traditional, heuristic algorithms for these two tasks. Combinatorial optimization approaches can deliver optimal solutions according to a model, can precisely capture trade-offs between conflicting decisions, and are more flexible at the expense of increased compilation time. This paper provides an exhaustive literature review and a classification of combinatorial optimization approaches to register allocation and instruction scheduling, with a focus on the techniques that are most applied in this context: integer programming, constraint programming, partitioned Boolean quadratic programming, and enumeration. Researchers in compilers and combinatorial optimization can benefit from identifying developments, trends, and challenges in the area; compiler practitioners may discern opportunities and grasp the potential benefit of applying combinatorial optimization