MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR

As the device dimensions have reduced from micrometer to nanometer range, new bulk silicon devices are now facing many undesirable effects of scaling leading device engineers to look for new process technologies. Silicon-on-insulator (SOI) has emerged as a very promising candidate for resolving the major problems plaguing the bulk silicon technology. G4FET [G4FET] is a SOI transistor with four independent gates. Although G4FET has already shown great potential in different applications, the widespread adoption of a technology in circuit design is heavily dependent upon good SPICE (Simulation Program with Integrated Circuit Emphasis) models. CAD (Computer Aided Design) tools are now ubiquitous in circuit design and a fast, robust and accurate SPICE model is absolutely necessary to transform G4FET into a mainstream technology. The research goal is to develop suitable SPICE models for G4FET to aid circuit designers in designing innovative analog and digital circuits using this new transistor. The first phase of this work is numerical modeling of the G4FET where four different numerical techniques are implemented, each with its merits and demerits. The first two methods are based on multivariate Lagrange interpolation and multidimensional Bernstein polynomial. The third numerical technique is based on multivariate regression polynomial to aid modeling with dense gridded data. Another suitable alternative namely multidimensional linear and cubic spline interpolation is explored as the fourth numerical modeling approach to solve some of the problems resulting from single polynomial approximation. The next phase of modeling involves developing a macromodel combining already existing SPICE models of MOSFET (metal–oxide–semiconductor field-effect transistor) and JFET (junction-gate field-effect transistor). This model is easy to implement in circuit simulators and provides good results compared to already demonstrated experimental works with innovative G4FET circuits. The final phase of this work involves the development of a physics-based compact model of G4FET with some empirical fitting parameters. A model for depletion-all-around operation is implemented in circuit simulator based on previous work. Another simplified model, combining MOS and JFET action, is implemented in circuit simulator to model the accumulation mode operation of G4FET

Statistical library characterization using belief propagation across multiple technology nodes

In this paper, we propose a novel flow to enable computationally efficient statistical characterization of delay and slew in standard cell libraries. The distinguishing feature of the proposed method is the usage of a limited combination of output capacitance, input slew rate and supply voltage for the extraction of statistical timing metrics of an individual logic gate. The efficiency of the proposed flow stems from the introduction of a novel, ultra-compact, nonlinear, analytical timing model, having only four universal regression parameters. This novel model facilitates the use of maximum-a-posteriori belief propagation to learn the prior parameter distribution for the parameters of the target technology from past characterizations of library cells belonging to various other technologies, including older ones. The framework then utilises Bayesian inference to extract the new timing model parameters using an ultra-small set of additional timing measurements from the target technology. The proposed method is validated and benchmarked on several production-level cell libraries including a state-of-the-art 14-nm technology node and a variation-aware, compact transistor model. For the same accuracy as the conventional lookup-table approach, this new method achieves at least 15x reduction in simulation runs.Masdar Institute of Science and Technology (Massachusetts Institute of Technology Cooperative Agreement

High Linearity Millimeter Wave Power Amplifiers with Novel Linearizer Techniques

Millimeter-wave communications have experienced phenomenal growth in recent years when limited frequency spectrum is occupied by the ever-developing communication services. The power amplifier, as the key component in the transmitter/receiver module of communication systems, affects performance of the whole system directly and receives much attention. For minimized distortion and optimum system performance, the non-constant en- velope modulation schemes used in communication systems have challenging requirements on linearity. As linearity is related to communication quality directly, several linearization techniques, such as predistortion and feedforward, are applied to power amplifier design. Predistortion method has the advantages over other techniques in relatively simple struc- ture and reasonable linearity improvement. But current predistortion circuits have quite limited performance improvement and relatively large insertion loss, which indicate the need for further research. In most of millimeter-wave amplifier design, great effort has been spent on output power or gain, while linearity is often ignored. As almost all the predistortion circuits operate at the RF frequencies, the linearized millimeter-wave com- munication circuit is still relatively immature and very challenging. This project is dedicated to solve the linearity problem faced by millimeter-wave power amplifier in communication systems, which lacks of e®ective techniques in this field. Linearity improvement with the predistortion method will be the key issue in this project and some original ideas for predistortion circuit design will be applied to millimeter-wave amplifiers. In this thesis, several predistortion circuits with novel structure were proposed, which provide a new approach for linearity improvement for millimeter-wave power am- plifier. A millimeter-wave power ampli¯er for LMDS applications built on GaAs pHEMT technology was developed to a high engineering standard, which works as the test bench for linearization. Actual operation and parasitic elements at tens of gigahertz have been taken into consideration during the design. Firstly, two novel predistorter structures based on the amplifier were proposed, one is based on an amplifier with a fixed bias circuit and the other is based on an amplifier with a nonlinear signal dependant bias circuit. These novel structures can improve the linearity while improving other metrics simultaneously, which can effectively solve the problem of insertion loss faced by the conventional structures. Besides this, an original predistortion circuit design methodology derived from frequency to signal amplitude transformation was proposed. Based on this methodology, several transfer functions were proposed and related predistortion circuits were built to linearize the power amplifier. As this methodology is quite different from the traditional approach, it can improve the linearity signifficantly while other metrics are affected slightly and has a broad prospect for application

High Linearity Millimeter Wave Power Amplifiers with Novel Linearizer Techniques

Millimeter-wave communications have experienced phenomenal growth in recent years when limited frequency spectrum is occupied by the ever-developing communication services. The power amplifier, as the key component in the transmitter/receiver module of communication systems, affects performance of the whole system directly and receives much attention. For minimized distortion and optimum system performance, the non-constant en- velope modulation schemes used in communication systems have challenging requirements on linearity. As linearity is related to communication quality directly, several linearization techniques, such as predistortion and feedforward, are applied to power amplifier design. Predistortion method has the advantages over other techniques in relatively simple struc- ture and reasonable linearity improvement. But current predistortion circuits have quite limited performance improvement and relatively large insertion loss, which indicate the need for further research. In most of millimeter-wave amplifier design, great effort has been spent on output power or gain, while linearity is often ignored. As almost all the predistortion circuits operate at the RF frequencies, the linearized millimeter-wave com- munication circuit is still relatively immature and very challenging. This project is dedicated to solve the linearity problem faced by millimeter-wave power amplifier in communication systems, which lacks of e®ective techniques in this field. Linearity improvement with the predistortion method will be the key issue in this project and some original ideas for predistortion circuit design will be applied to millimeter-wave amplifiers. In this thesis, several predistortion circuits with novel structure were proposed, which provide a new approach for linearity improvement for millimeter-wave power am- plifier. A millimeter-wave power ampli¯er for LMDS applications built on GaAs pHEMT technology was developed to a high engineering standard, which works as the test bench for linearization. Actual operation and parasitic elements at tens of gigahertz have been taken into consideration during the design. Firstly, two novel predistorter structures based on the amplifier were proposed, one is based on an amplifier with a fixed bias circuit and the other is based on an amplifier with a nonlinear signal dependant bias circuit. These novel structures can improve the linearity while improving other metrics simultaneously, which can effectively solve the problem of insertion loss faced by the conventional structures. Besides this, an original predistortion circuit design methodology derived from frequency to signal amplitude transformation was proposed. Based on this methodology, several transfer functions were proposed and related predistortion circuits were built to linearize the power amplifier. As this methodology is quite different from the traditional approach, it can improve the linearity signifficantly while other metrics are affected slightly and has a broad prospect for application

Designers manual for circuit design by analog/digital techniques Final report

Manual for designing circuits by hybrid compute

FPGA ARCHITECTURE AND VERIFICATION OF BUILT IN SELF-TEST (BIST) FOR 32-BIT ADDER/SUBTRACTER USING DE0-NANO FPGA AND ANALOG DISCOVERY 2 HARDWARE

The integrated circuit (IC) is an integral part of everyday modern technology, and its application is very attractive to hardware and software design engineers because of its versatility, integration, power consumption, cost, and board area reduction. IC is available in various types such as Field Programming Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), System on Chip (SoC) architecture, Digital Signal Processing (DSP), microcontrollers (μC), and many more. With technology demand focused on faster, low power consumption, efficient IC application, design engineers are facing tremendous challenges in developing and testing integrated circuits that guaranty functionality, high fault coverage, and reliability as the transistor technology is shrinking to the point where manufacturing defects of ICs are affecting yield which associates with the increased cost of the part. The competitive IC market is pressuring manufactures of ICs to develop and market IC in a relatively quick turnaround which in return requires design and verification engineers to develop an integrated self-test structure that would ensure fault-free and the quality product is delivered on the market. 70-80% of IC design is spent on verification and testing to ensure high quality and reliability for the enduser. To test complex and sophisticated IC designs, the verification engineers must produce laborious and costly test fixtures which affect the cost of the part on the competitive market. To avoid increasing the part cost due to yield and test time to the end-user and to keep up with the competitive market many IC design engineers are deviating from complex external test fixture approach and are focusing on integrating Built-in Self-Test (BIST) or Design for Test (DFT) techniques onto IC’s which would reduce time to market but still guarantee high coverage for the product. Understanding the BIST, the architecture, as well as the application of IC, must be understood before developing IC. The architecture of FPGA is elaborated in this paper followed by several BIST techniques and applications of those BIST relative to FPGA, SoC, analog to digital (ADC), or digital to analog converters (DAC) that are integrated on IC. Paper is concluded with verification of BIST for the 32-bit adder/subtracter designed in Quartus II software using the Analog Discovery 2 module as stimulus and DE0-NANO FPGA board for verification

CMOS digital pixel sensor array with time domain analogue to digital conversion

This thesis presents a digital pixel sensor array, which is the first stage of an ongoing project to produce a CMOS image sensor with on-chip image processing. The analogue to digital conversion is performed at the pixel level, with the result stored in pixel memory. This architecture allows fast, reliable access to the image data and simplifies the integration of the image array and the processing logic. Each pixel contains a photodiode sensor, a comparator, memory and addressing logic. The photodiode sensor operates in integrating mode, where the photodiode junction capacitance is first charged to an initial voltage, and then discharged by the photodiode leakage current, which is comprised mainly of optically generated carriers. The analogue to digital conversion is performed by measuring the time taken for the photodiode cathode voltage to fall from its initial voltage, to the comparator reference voltage. This triggers the 8-bit pixel memory, which stores a data value representative of the time. The trigger signal also resets the photodiode, which conserves the charge stored in the junction capacitance, and also prevents blooming. An on-chip control circuit generates the digital data that is distributed globally to the array. The control circuit compensates for the inverse relationship between the integration time and the photocurrent by adjusting the data clock timing. The period of the data clock is increased at the same rate as the integration time, resulting in a linear relationship between the digital data and the photocurrent. The design is realised as a 64 x 64 pixel array, manufactured in O.35µm 3.3 V CMOS technology. Each pixel occupies an area of 45µm x 45µm with a 12.3% fill factor, and the entire pixel array and control circuit measures 3.7mm x 3.9mm. Experimental results confirm the operation of the digital pixel, and the linearising control circuit. The digital pixel has a dynamic range of 85dB, and can be adapted to different lighting conditions by varying a single clock frequency. The data captured by the array can be randomly accessed, and is read from the array nondestructivcly

Spread spectrum modulation system for burst mode DC-DC converters

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (leaves 91-92).This thesis develops a spread spectrum switching system for DC-DC converters operating in burst mode. Burst mode DC-DC converters have high efficiency under low-power conditions in applications such as cell phones and notebook computers, but often produce noise in the audible range. This thesis explores a frequency modulation scheme and transient control that attenuates audible noise harmonics while minimizing the tradeoff for converter regulation, efficiency, and output voltage ripple.by Ji Zhang.M.Eng

Bridging the Gap between Physical and Circuit Analysis for Variability-Aware Microwave Design: Modeling Approaches

Process-induced variability is a growing concern in the design of analog circuits, and in particular for monolithic microwave integrated circuits (MMICs) targeting the 5G and 6G communication systems. The RF and microwave (MW) technologies developed for the deployment of these communication systems exploit devices whose dimension is now well below 100 nm, featuring an increasing variability due to the fabrication process tolerances and the inherent statistical behavior of matter at the nanoscale. In this scenario, variability analysis must be incorporated into circuit design and optimization, with ad hoc models retaining a direct link to the fabrication process and addressing typical MMIC nonlinear applications like power amplification and frequency mixing. This paper presents a flexible procedure to extract black-box models from accurate physics-based simulations, namely TCAD analysis of the active devices and EM simulations for the passive structures, incorporating the dependence on the most relevant fabrication process parameters. We discuss several approaches to extract these models and compare them to highlight their features, both in terms of accuracy and of ease of extraction. We detail how these models can be implemented into EDA tools typically used for RF and MMIC design, allowing for fast and accurate statistical and yield analysis. We demonstrate the proposed approaches extracting the black-box models for the building blocks of a power amplifier in a GaAs technology for X-band applications

The Magnetic Electron Ion Spectrometer (MagEIS) Instruments Aboard the Radiation Belt Storm Probes (RBSP) Spacecraft

This paper describes the Magnetic Electron Ion Spectrometer (MagEIS) instruments aboard the RBSP spacecraft from an instrumentation and engineering point of view. There are four magnetic spectrometers aboard each of the two spacecraft, one low-energy unit (20–240 keV), two medium-energy units (80–1200 keV), and a high-energy unit (800–4800 keV). The high unit also contains a proton telescope (55 keV–20 MeV). The magnetic spectrometers focus electrons within a selected energy pass band upon a focal plane of several silicon detectors where pulse-height analysis is used to determine if the energy of the incident electron is appropriate for the electron momentum selected by the magnet. Thus each event is a two-parameter analysis, an approach leading to a greatly reduced background. The physics of these instruments are described in detail followed by the engineering implementation. The data outputs are described, and examples of the calibration results and early flight data presented