Synthesizable delay line architectures for digitally controlled voltage regulators

Voltage regulators used in the integrated circuit (IC) industry require precise voltage regulation. In digitally controlled switching converters, this precise voltage regulation is achieved by high resolution digital pulse width modulators (DPWM). Digital delay lines can be used to generate the pulse width modulation (PWM) signal. Conventional delay lines are designed in a full custom design methodology which is extremely slow and expensive compared to register-transfer level (RTL) based designs; also RTL based designs are technology independent so the same design can be used with new technologies. The purpose of this work is to introduce a new architecture for the fully synthesizable digital delay line used in digitally controlled voltage regulators. A comparison between the proposed scheme and the conventional delay line is done post synthesis on the key delay line specifications like linearity, area, complexity, and compensation for process, voltage, and temperature (PVT) variations for multiple clock frequencies. Both schemes are designed using a hardware description language (HDL) and synthesized using Intel 32nm technology. The comparison showed that the proposed architecture has better linearity, area, and also it has a fast calibration time with respect to conventional delay lines. The delay lines are designed in parameterized way in order to make the design suitable for multiple frequencies

Re-thinking Analog Integrated Circuits in Digital Terms: A New Design Concept for the IoT Era

A steady trend towards the design of mostly-digital and digital-friendly analog circuits, suitable to integration in mainstream nanoscale CMOS by a highly automated design flow, has been observed in the last years to address the requirements of the emerging Internet of Things (IoT) applications. In this context, this tutorial brief presents an overview of concepts and design methodologies that emerged in the last decade, aimed to the implementation of analog circuits like Operational Transconductance Amplifiers, Voltage References and Data Converters by digital circuits. The current design challenges and application scenarios as well as the future perspectives and opportunities in the field of digital-based analog processing are finally discussed

Relaxation Digital-to-Analog Converter with Foreground Digital Self-Calibration

3noA reference-free, fully digital foreground self-calibration strategy intended to automatically tune the clock frequency of Relaxation Digital to Analog Converters (ReDACs), as demanded for linear operation, is presented in this paper. The effectiveness of the proposed approach is demonstrated by computer simulations on a 10-bit, 2MS/s ReDAC designed in 40nm CMOS and operated from a 600mV power supply voltage. After the proposed calibration, the ReDAC is shown to operate near the optimal clock frequency achieving 0.98 LSB maximum INL, 1.00 LSB maximum DNL and 9.06 ENOB.partially_openopenPaolo Crovetti; Roberto Rubino; Francesco MusolinoCrovetti, PAOLO STEFANO; Rubino, Roberto; Musolino, Francesc

Rapid SoC Design: On Architectures, Methodologies and Frameworks

Modern applications like machine learning, autonomous vehicles, and 5G networking require an order of magnitude boost in processing capability. For several decades, chip designers have relied on Moore’s Law - the doubling of transistor count every two years to deliver improved performance, higher energy efficiency, and an increase in transistor density. With the end of Dennard’s scaling and a slowdown in Moore’s Law, system architects have developed several techniques to deliver on the traditional performance and power improvements we have come to expect. More recently, chip designers have turned towards heterogeneous systems comprised of more specialized processing units to buttress the traditional processing units. These specialized units improve the overall performance, power, and area (PPA) metrics across a wide variety of workloads and applications. While the GPU serves as a classical example, accelerators for machine learning, approximate computing, graph processing, and database applications have become commonplace. This has led to an exponential growth in the variety (and count) of these compute units found in modern embedded and high-performance computing platforms. The various techniques adopted to combat the slowing of Moore’s Law directly translates to an increase in complexity for modern system-on-chips (SoCs). This increase in complexity in turn leads to an increase in design effort and validation time for hardware and the accompanying software stacks. This is further aggravated by fabrication challenges (photo-lithography, tooling, and yield) faced at advanced technology nodes (below 28nm). The inherent complexity in modern SoCs translates into increased costs and time-to-market delays. This holds true across the spectrum, from mobile/handheld processors to high-performance data-center appliances. This dissertation presents several techniques to address the challenges of rapidly birthing complex SoCs. The first part of this dissertation focuses on foundations and architectures that aid in rapid SoC design. It presents a variety of architectural techniques that were developed and leveraged to rapidly construct complex SoCs at advanced process nodes. The next part of the dissertation focuses on the gap between a completed design model (in RTL form) and its physical manifestation (a GDS file that will be sent to the foundry for fabrication). It presents methodologies and a workflow for rapidly walking a design through to completion at arbitrary technology nodes. It also presents progress on creating tools and a flow that is entirely dependent on open-source tools. The last part presents a framework that not only speeds up the integration of a hardware accelerator into an SoC ecosystem, but emphasizes software adoption and usability.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/168119/1/ajayi_1.pd

Digital-based analog processing in nanoscale CMOS ICs for IoT applications

The Internet-of-Things (IoT) concept has been opening up a variety of applications, such as urban and environmental monitoring, smart health, surveillance, and home automation. Most of these IoT applications require more and more power/area efficient Complemen tary Metal–Oxide–Semiconductor (CMOS) systems and faster prototypes (lower time-to market), demanding special modifications in the current IoT design system bottleneck: the analog/RF interfaces. Specially after the 2000s, it is evident that there have been significant improvements in CMOS digital circuits when compared to analog building blocks. Digital circuits have been taking advantage of CMOS technology scaling in terms of speed, power consump tion, and cost, while the techniques running behind the analog signal processing are still lagging. To decrease this historical gap, there has been an increasing trend in finding alternative IC design strategies to implement typical analog functions exploiting Digital in-Concept Design Methodologies (DCDM). This idea of re-thinking analog functions in digital terms has shown that Analog ICs blocks can also avail of the feature-size shrinking and energy efficiency of new technologies. This thesis deals with the development of DCDM, demonstrating its compatibility for Ultra-Low-Voltage (ULV) and Power (ULP) IoT applications. This work proves this state ment through the proposing of new digital-based analog blocks, such as an Operational Transconductance Amplifiers (OTAs) and an ac-coupled Bio-signal Amplifier (BioAmp). As an initial contribution, for the first time, a silicon demonstration of an embryonic Digital-Based OTA (DB-OTA) published in 2013 is exhibited. The fabricated DB-OTA test chip occupies a compact area of 1,426 µm2 , operating at supply voltages (VDD) down to 300 mV, consuming only 590 pW while driving a capacitive load of 80pF. With a Total Harmonic Distortion (THD) lower than 5% for a 100mV input signal swing, its measured small-signal figure of merit (FOMS) and large-signal figure of merit (FOML) are 2,101 V −1 and 1,070, respectively. To the best of this thesis author’s knowledge, this measured power is the lowest reported to date in OTA literature, and its figures of merit are the best in sub-500mV OTAs reported to date. As the second step, mainly due to the robustness limitation of previous DB-OTA, a novel calibration-free digital-based topology is proposed, named here as Digital OTA (DIG OTA). A 180-nm DIGOTA test chip is also developed exhibiting an area below the 1000 µm2 wall, 2.4nW power under 150pF load, and a minimum VDD of 0.25 V. The proposed DIGOTA is more digital-like compared with DB-OTA since no pseudo-resistor is needed. As the last contribution, the previously proposed DIGOTA is then used as a building block to demonstrate the operation principle of power-efficient ULV and ultra-low area (ULA) fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA) such as extreme low area Body Dust. Measured results in 180nm CMOS confirm that the proposed BioDIGOTA can work with a supply voltage down to 400 mV, consuming only 95 nW. The BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22X times compared to the current state of the art while keeping reasonable system performance, such as 7.6 Noise Efficiency Factor (NEF) with 1.25 µVRMS input-referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of the common-mode rejection ratio (CMRR) and 55 dB of power supply rejection ratio (PSRR). After reviewing the current DCDM trend and all proposed silicon demonstrations, the thesis concludes that, despite the current analog design strategies involved during the analog block development

LOW-JITTER AND LOW-SPUR RING-OSCILLATOR-BASED PHASE-LOCKED LOOPS

Department of Electrical EngineeringIn recent years, ring-oscillator based clock generators have drawn a lot of attention due to the merits of high area efficiency, potentially wide tuning range, and multi-phase generation. However, the key challenge is how to suppress the poor jitter of ring oscillators. There have been many efforts to develop a ring-oscillator-based clock generator targeting very low-jitter performance. However, it remains difficult for conventional architectures to achieve both low RMS jitter and low levels of reference spurs concurrently while having a high multiplication factor. In this dissertation, a time-domain analysis is presented that provides an intuitive understanding of RMS jitter calculation of the clock generators from their phase-error correction mechanisms. Based on this analysis, we propose new designs of a ring-oscillator-based PLL that addresses the challenges of prior-art ring-based architectures. This dissertation introduces a ring-oscillator-based PLL with the proposed fast phase-error correction (FPEC) technique, which emulates the phase-realignment mechanism of an injection-locked clock multiplier (ILCM). With the FPEC technique, the phase error of the voltage-controlled oscillator (VCO) is quickly removed, achieving ultra-low jitter. In addition, in the transfer function of the proposed architecture, an intrinsic integrator is involved since it is naturally based on a PLL topology. The proposed PLL can thus have low levels of reference spurs while maintaining high stability even for a large multiplication factor. Furthermore, it presents another design of a digital PLL embodying the FPEC technique (or FPEC DPLL). To overcome the problem of a conventional TDC, a low-power optimally-spaced (OS) TDC capable of effectively minimizing the quantization error is presented. In the proposed FPEC DPLL, background digital controllers continuously calibrate the decision thresholds and the gain of the error correction by the loop to be optimal, thus dramatically reducing the quantization error. Since the proposed architecture is implemented in a digital fashion, the variables defining the characteristics of the loop can be easily estimated and calibrated by digital calibrators. As a result, the performances of an ultra-low jitter and the figure-of-merit can be achieved.clos

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Power Management Circuits for Energy Harvesting Applications

Energy harvesting is the process of converting ambient available energy into usable electrical energy. Multiple types of sources are can be used to harness environmental energy: solar cells, kinetic transducers, thermal energy, and electromagnetic waves. This dissertation proposal focuses on the design of high efficiency, ultra-low power, power management units for DC energy harvesting sources. New architectures and design techniques are introduced to achieve high efficiency and performance while achieving maximum power extraction from the sources. The first part of the dissertation focuses on the application of inductive switching regulators and their use in energy harvesting applications. The second implements capacitive switching regulators to minimize the use of external components and present a minimal footprint solution for energy harvesting power management. Analysis and theoretical background for all switching regulators and linear regulators are described in detail. Both solutions demonstrate how low power, high efficiency design allows for a self-sustaining, operational device which can tackle the two main concerns for energy harvesting: maximum power extraction and voltage regulation. Furthermore, a practical demonstration with an Internet of Things type node is tested and positive results shown by a fully powered device from harvested energy. All systems were designed, implemented and tested to demonstrate proof-of-concept prototypes

Self-Calibrated, Low-Jitter and Low-Reference-Spur Injection-Locked Clock Multipliers

Department of Electrical EngineeringThis dissertation focuses primarily on the design of calibrators for the injection-locked clock multiplier (ILCM). ILCMs have advantage to achieve an excellent jitter performance at low cost, in terms of area and power consumption. The wide loop bandwidth (BW) of the injection technique could reject the noise of voltage-controlled oscillator (VCO), making it thus suitable for the rejection of poor noise of a ring-VCO and a high frequency LC-VCO. However, it is difficult to use without calibrators because of its sensitiveness in process-voltage-temperature (PVT) variations. In Chapter 2, conventional frequency calibrators are introduced and discussed. This dissertation introduces two types of calibrators for low-power high-frequency LC-VCO-based ILFMs in Chapter 3 and Chapter 4 and high-performance ring-VCO-based ILCM in Chapter 5. First, Chapter 3 presents a low power and compact area LC-tank-based frequency multiplier. In the proposed architecture, the input signals have a pulsed waveform that involves many high-order harmonics. Using an LC-tank that amplifies only the target harmonic component, while suppressing others, the output signal at the target frequency can be obtained. Since the core current flows for a very short duration, due to the pulsed input signals, the average power consumption can be dramatically reduced. Effective removal of spurious tones due to the damping of the signal is achieved using a limiting amplifier. In this work, a prototype frequency tripler using the proposed architecture was designed in a 65 nm CMOS process. The power consumption was 950 ??W, and the active area was 0.08 mm2. At a 3.12 GHz frequency, the phase noise degradation with respect to the theoretical bound was less than 0.5 dB. Second, Chapter 4 presents an ultra-low-phase-noise ILFM for millimeter wave (mm-wave) fifth-generation (5G) transceivers. Using an ultra-low-power frequency-tracking loop (FTL), the proposed ILFM is able to correct the frequency drifts of the quadrature voltage-controlled oscillator of the ILFM in a real-time fashion. Since the FTL is monitoring the averages of phase deviations rather than detecting or sampling the instantaneous values, it requires only 600??W to continue to calibrate the ILFM that generates an mm-wave signal with an output frequency from 27 to 30 GHz. The proposed ILFM was fabricated in a 65-nm CMOS process. The 10-MHz phase noise of the 29.25-GHz output signal was ???129.7 dBc/Hz, and its variations across temperatures and supply voltages were less than 2 dB. The integrated phase noise from 1 kHz to 100 MHz and the rms jitter were???39.1 dBc and 86 fs, respectively. Third, Chapter 5 presents a low-jitter, low-reference-spur ring voltage-controlled oscillator (ring VCO)-based ILCM. Since the proposed triple-point frequency/phase/slope calibrator (TP-FPSC) can accurately remove the three root causes of the frequency errors of ILCMs (i.e., frequency drift, phase offset, and slope modulation), the ILCM of this work is able to achieve a low-level reference spur. In addition, the calibrating loop for the frequency drift of the TP-FPSC offers an additional suppression to the in-band phase noise of the output signal. This capability of the TP-FPSC and the naturally wide bandwidth of the injection-locking mechanism allows the ILCM to achieve a very low RMS jitter. The ILCM was fabricated in a 65-nm CMOS technology. The measured reference spur and RMS jitter were ???72 dBc and 140 fs, respectively, both of which are the best among the state-of-the-art ILCMs. The active silicon area was 0.055 mm2, and the power consumption was 11.0 mW.clos

Low-Power Reconfigurable Sensing Circuitry for the Internet-of-Things Paradigm

With ubiquitous wireless communication via Wi-Fi and nascent 5th Generation mobile communications, more devices -- both smart and traditionally dumb -- will be interconnected than ever before. This burgeoning trend is referred to as the Internet-of-Things. These new sensing opportunities place a larger burden on the underlying circuitry that must operate on finite battery power and/or within energy-constrained environments. New developments of low-power reconfigurable analog sensing platforms like field-programmable analog arrays (FPAAs) present an attractive sensing solution by processing data in the analog domain while staying flexible in design. This work addresses some of the contemporary challenges of low-power wireless sensing via traditional application-specific sensing and with FPAAs. A large emphasis is placed on furthering the development of FPAAs by making them more accessible to designers without a strong integrated-circuit background -- much like FPGAs have done for digital designers