Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios

Next-generation wireless communication systems put more stringent performance requirements on the wireless RF receiver circuits. Sensitivity, linearity, bandwidth and power consumption are some of the most important specifications that often face tightly coupled tradeoffs between them. To increase the data throughput, a large number of fragmented spectrums are being introduced to the wireless communication standards. Carrier aggregation technology needs concurrent communication across several non-contiguous frequency bands, which results in a rapidly growing number of band combinations. Supporting all the frequency bands and their aggregation combinations increases the complexity of the RF receivers. Highly flexible software defined radio (SDR) is a promising technology to address these applications scenarios with lower complexity by relaxing the specifications of the RF filters or eliminating them. However, there are still many technology challenges with both the receiver architecture and the circuit implementations. The performance requirements of the receivers can also vary across different application scenario and RF environments. Field-programmable dynamic performance tradeoff can potentially reduce the power consumption of the receiver. In this dissertation, we address the performance enhancement challenges in the wideband SDRs by innovations at both the circuit building block level and the receiver architecture level. A series of research projects are conducted to push the state-of-the-art performance envelope and add features such as field-programmable performance tradeoff and concurrent reception. The projects originate from the concept of thermal noise canceling techniques and further enhance the RF performance and add features for more capable SDR receivers. Four generations of prototype LNA or receiver chips are designed, and each of them pushes at least one aspect of the RF performance such as bandwidth, linearity, and NF. A noise-canceling distributed LNA breaks the tradeoff between NF and RF bandwidth by introducing microwave circuit techniques from the distributed amplifiers. The LNA architecture uniquely provides ultra high bandwidth and low NF at low frequencies. A family of field-programmable LNA realized field-programmable performance tradeoff with current-reuse programmable transconductance cells. Interferer-reflecting loops can be applied around the LNAs to improve their input linearity by rejecting the out-of-band interferers with a wideband low in- put impedance. A low noise transconductance amplifier (LNTA) that operates in class-AB-C is invented to can handle rail-to-rail out-of-band blocker without saturation. Class-AB and class-C transconductors form a composite amplifier to increase the linear range of the input voltage. A new antenna interface named frequency-translational quadrature-hybrid (FTQH) breaks the input impedance matching requirement of the LNAs by introducing quadrature hybrid couplers to the CMOS RFIC design. The FTQH receiver achieves wideband sub-1dB NF and supports scalable massive frequency-agile concurrent reception

Switched-Capacitor RF Receivers for High Interferer Tolerance

The demand for broadband wireless communication is growing rapidly, requiring more spectrum resources. However, spectrum usage is inefficient today because different frequency bands are allocated for different communication standards and most of the bands are not highly occupied. Cognitive radio systems with dynamic spectrum access improve spectrum efficiency, but they require wideband tunable receiver hardware. In such a system, a preselect filter is required for the RF receiver front end, because an out-of-band (OB) interferer can block the front end or cause distortion, desensitizing the receiver. In a conventional solution, off-chip passive filters, such as surface-acoustic-wave (SAW) filters, are used to reject the OB interferer. However, such passive filters are hardly tunable, have large area, and are very expensive. On-chip, high-selectivity, linearly tunable RF filters are, therefore, a hot topic in RF front-end research. Switched-capacitor (SC) RF filters, such as N-path filters, feature good linearity and tunability, making them good candidates for tunable RF filters. However, N-path filters have some drawbacks: notably, a poor harmonic response and limited close-by blocker tolerance. This thesis presents the design and implementation of several interferer-tolerant receivers based on SC technology. We present an RF receiver with a harmonic-rejecting N-path filter to improve the harmonic response of the N-path bandpass filter. It features tunable narrowband filtering and high attenuation of the third- and fifth-order LO harmonics at the LNA output, which improves the blocker tolerance at LO harmonics. The 0.2-1 GHz RF receiver is implemented in a 65 nm CMOS process. The blocker 1 dB compression point (B1dB) is -2.4 dBm at a 20 MHz offset, and remains high at the third- and fifth-order LO harmonics. The LNA’s reverse isolation helps keep the LO emission below -90 dBm. A two-stage harmonic-rejection approach offers a > 51 dB harmonic-rejection ratio at the third- and fifth-order LO harmonics without calibration. To improve tolerance for close-by blockers, we further present an SC RF receiver achieving high-order, tunable, highly linear RF filtering. We implement RF input impedance matching, N-path filtering, high-order discrete-time infinite-impulse response (IIR) filtering and downconversion using only switches and capacitors in a 0.1-0.7 GHz prototype with tunable center frequency, programmable filter order, and very high tolerance for OB blockers. The 40 nm CMOS receiver consumes 38.5-76.5mA, achieves 40 dB gain, 24 dBm OB IIP3, 14.7 dBm B1dB for a 30MHz blocker offset, 6.8-9.7 dB noise figure, and > 66dB calibrated harmonic rejection ratio. The key drawback of our earlier SC receiver is the relatively high theoretical lower limit of the noise figure. To improve the noise performance, we developed a 0.1-0.6 GHz chopping SC RF receiver with an integrated blocker detector. We achieve RF impedance matching, high-order OB interferer filtering, and flicker-noise chopping with passive SC circuits only. The 34-80 mW 65 nm receiver achieves 35 dB gain, 4.6-9 dB NF, 31 dBm OB-IIP3, and 15 dBm B1dB. The 0.2 mW integrated blocker detector detects large OB blockers with only a 1 us response time. The filter order can be adapted to blocker power with the blocker detector

Surpassing Fundamental Limits through Time Varying Electromagnetics

Surpassing the fundamental limits that govern all electromagnetic structures, such as reciprocity and the delay-bandwidth-size limit, will have a transformative impact on all applications based on electromagnetic circuits and systems. For instance, violating principles of reciprocity enables non-reciprocal components such as isolators and circulators, which find application in full-duplex wireless radios, radar, biomedical imaging, and quantum computing systems. Overcoming the delay-bandwidth-size limit enables ultra-broadband yet extremely-compact devices whose size is not fundamentally related to the wavelength at the operating frequency. The focus of this dissertation is on using time-variance as a new toolbox to overcome these fundamental limits and re-imagine circuit and system design. Traditional non-reciprocal components are realized using ferrite materials that loose their reciprocity under the application of external magnetic bias. However, the sheer volume, cost and weight of these magnet based non-reciprocal components coupled with their inability to be fabricated in conventional semiconductor processes, have limited their application to bulky and large-scale systems. Other approaches such as active-biased and non-linearity based non-reciprocity are compatible with semiconductor processes, however, they suffer from other poor linearity and noise performance. In this dissertation, using passive transistor switch as the modulating element, we have proposed the concept of spatio-temporal conductivity modulation and have demonstrated a gamut of non-reciprocal devices ranging from gyrators to isolators and circulators. Through novel circuit topologies, for the first time, we have demonstrated on-chip circulators with multi-watt input power handling, operation at high millimeter-wave frequencies, and tailor made circulators for emerging technologies such as simultaneous-transmit-and-receive MRI and quantum computing. Delay-bandwidth-size trade-off is another fundamental electromagnetic limit, that constrains the delay imparted by a medium or a device within a fixed footprint to be inversely proportional to the signal bandwidth. It is this limit that governs the size of any microwave passive devices to be inversely proportional to its operating frequency. As a part of this dissertation, through intelligent clocking of switched capacitor networks we overcame the delay-bandwidth-size limit, thus resulting in infinitesimal, yet broadband microwave devices. Here we proposed a new paradigm in wave propagation where the properties such as the propagation delay and characteristic impedance does not depend on the constituent elements/materials of the medium, but rather heavily rely on the user-defined modulation scheme, thereby opening huge opportunities for realizing highly-reconfigurable passives. Leveraging these concepts, we demonstrated wide range of reciprocal an non-reciprocal devices including ultra-compact delay elements, highly-reconfigurable microwave passives, ultra-wideband circulators with infinitesimal form-factors and dispersion-free chip scale floquet topological insulators. Application of these devices have also been evaluated in real-world systems through our demonstrations of wideband, full-duplex receivers leveraging switched capacitors based true-time-delay interference cancelers and floquet topological insulator based antenna interfaces for full-duplex phased-arrays and ultra-wideband beamformers. Furthermore, to cater the growing RF and microwave needs of future, large-scale quantum computing systems, we demonstrated a low-cryogenic, wideband circulator based on time modulation of superconducting devices. This superconducting circulator is expected to operate alongside the superconducting qubits, inside a dilution refrigerator at 10mK-100mK, thus enabling a tightly integrated quantum system. We also presented the design and implementation of a cryogenic-CMOS clock driver chip that will generate the clocks required by the superconducting circulator. Finally, we also demonstrated the design and implementation of a low-noise, low power consumption, 6GHz - 8GHz cryogenic downconversion receiver at 4K for cryogenic qubit readout

Ultra-low-power circuits and systems for wearable and implantable medical devices

Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (pages 219-231).Advances in circuits, sensors, and energy storage elements have opened up many new possibilities in the health industry. In the area of wearable devices, the miniaturization of electronics has spurred the rapid development of wearable vital signs, activity, and fitness monitors. Maximizing the time between battery recharge places stringent requirements on power consumption by the device. For implantable devices, the situation is exacerbated by the fact that energy storage capacity is limited by volume constraints, and frequent battery replacement via surgery is undesirable. In this case, the design of energy-efficient circuits and systems becomes even more crucial. This thesis explores the design of energy-efficient circuits and systems for two medical applications. The first half of the thesis focuses on the design and implementation of an ultra-low-power, mixed-signal front-end for a wearable ECG monitor in a 0.18pm CMOS process. A mixed-signal architecture together with analog circuit optimizations enable ultra-low-voltage operation at 0.6V which provides power savings through voltage scaling, and ensures compatibility with state-of-the-art DSPs. The fully-integrated front-end consumes just 2.9[mu]W, which is two orders of magnitude lower than commercially available parts. The second half of this thesis focuses on ultra-low-power system design and energy-efficient neural stimulation for a proof-of-concept fully-implantable cochlear implant. First, implantable acoustic sensing is demonstrated by sensing the motion of a human cadaveric middle ear with a piezoelectric sensor. Second, alternate energy-efficient electrical stimulation waveforms are investigated to reduce neural stimulation power when compared to the conventional rectangular waveform. The energy-optimal waveform is analyzed using a computational nerve fiber model, and validated with in-vivo ECAP recordings in the auditory nerve of two cats and with psychophysical tests in two human cochlear implant users. Preliminary human subject testing shows that charge and energy savings of 20-30% and 15-35% respectively are possible with alternative waveforms. A system-on-chip comprising the sensor interface, reconfigurable sound processor, and arbitrary-waveform neural stimulator is implemented in a 0.18[mu]m high-voltage CMOS process to demonstrate the feasibility of this system. The sensor interface and sound processor consume just 12[mu]W of power, representing just 2% of the overall system power which is dominated by stimulation. As a result, the energy savings from using alternative stimulation waveforms transfer directly to the system.by Marcus Yip.Ph.D

Integrated RF oscillators and LO signal generation circuits

This thesis deals with fully integrated LC oscillators and local oscillator (LO) signal generation circuits. In communication systems a good-quality LO signal for up- and down-conversion in transmitters is needed. The LO signal needs to span the required frequency range and have good frequency stability and low phase noise. Furthermore, most modern systems require accurate quadrature (IQ) LO signals. This thesis tackles these challenges by presenting a detailed study of LC oscillators, monolithic elements for good-quality LC resonators, and circuits for IQ-signal generation and for frequency conversion, as well as many experimental circuits. Monolithic coils and variable capacitors are essential, and this thesis deals with good structures of these devices and their proper modeling. As experimental test devices, over forty monolithic inductors and thirty varactors have been implemented, measured and modeled. Actively synthesized reactive elements were studied as replacements for these passive devices. At first glance these circuits show promising characteristics, but closer noise and nonlinearity analysis reveals that these circuits suffer from high noise levels and a small dynamic range. Nine circuit implementations with various actively synthesized variable capacitors were done. Quadrature signal generation can be performed with three different methods, and these are analyzed in the thesis. Frequency conversion circuits are used for alleviating coupling problems or to expand the number of frequency bands covered. The thesis includes an analysis of single-sideband mixing, frequency dividers, and frequency multipliers, which are used to perform the four basic arithmetical operations for the frequency tone. Two design cases are presented. The first one is a single-sideband mixing method for the generation of WiMedia UWB LO-signals, and the second one is a frequency conversion unit for a digital period synthesizer. The last part of the thesis presents five research projects. In the first one a temperature-compensated GaAs MESFET VCO was developed. The second one deals with circuit and device development for an experimental-level BiCMOS process. A cable-modem RF tuner IC using a SiGe process was developed in the third project, and a CMOS flip-chip VCO module in the fourth one. Finally, two frequency synthesizers for UWB radios are presented

Integrated Self-Interference Cancellation for Full-Duplex and Frequency-Division Duplexing Wireless Communication Systems

From wirelessly connected robots to car-to-car communications, and to smart cities, almost every aspect of our lives will benefit from future wireless communications. While promise an exciting future world, next-generation wireless communications impose requirements on the data rate, spectral efficiency, and latency (among others) that are higher than those for today's systems by several orders of magnitude. Full-duplex wireless, an emergent wireless communications paradigm, breaks the long-held assumption that it is impossible for a wireless device to transmit and receive simultaneously at the same frequency, and has the potential to immediately double network capacity at the physical (PHY) layer and offers many other benefits (such as reduced latency) at the higher layers. Recently, discrete-component-based demonstrations have established the feasibility of full-duplex wireless. However, the realization of integrated full duplex radios, compact radios that can fit into smartphones, is fraught with fundamental challenges. In addition, to unleash the full potential of full-duplex communication, a careful redesign of the PHY layer and the medium access control (MAC) layer using a cross-layer approach is required. The biggest challenge associated with full duplex wireless is the tremendous amount of transmitter self-interference right on top of the desired signal. In this dissertation, new self-interference-cancellation approaches at both system and circuit levels are presented, contributing towards the realization of full-duplex radios using integrated circuit technology. Specifically, these new approaches involve elimination of the noise and distortion of the cancellation circuitry, enhancing the integrated cancellation bandwidth, and performing joint radio frequency, analog, and digital cancellation to achieve cancellation with nearly one part-per-billion accuracy. In collaboration with researchers at higher layers of the stack, a cross-layer approach has been used in our full-duplex research and has allowed us to derive power allocation algorithms and to characterize rate-gain improvements for full-duplex wireless networks. To enable experimental characterization of full-duplex MAC layer algorithms, a cross-layered software-defined full-duplex radio testbed has been developed. In collaboration with researchers from the field of micro-electro-mechanical systems, we demonstrate a multi-band frequency-division duplexing system using a cavity-filter-based tunable duplexer and our integrated widely-tunable self-interference-cancelling receiver

Neurocomputing systems for auditory processing

This thesis studies neural computation models and neuromorphic implementations of the auditory pathway with applications to cochlear implants and artificial auditory sensory and processing systems. Very low power analogue computation is addressed through the design of micropower analogue building blocks and an auditory preprocessing module targeted at cochlear implants. The analogue building blocks have been fabricated and tested in a standard Complementary Metal Oxide Silicon (CMOS) process. The auditory pre-processing module design is based on the cochlea signal processing mechanisms and low power microelectronic design methodologies. Compared to existing preprocessing techniques used in cochlear implants, the proposed design has a wider dynamic range and lower power consumption. Furthermore, it provides the phase coding as well as the place coding information that are necessary for enhanced functionality in future cochlear implants. The thesis presents neural computation based approaches to a number of signal-processing problems encountered in cochlear implants. Techniques that can improve the performance of existing devices are also presented. Neural network based models for loudness mapping and pattern recognition based channel selection strategies are described. Compared with state—of—the—art commercial cochlear implants, the thesis results show that the proposed channel selection model produces superior speech sound qualities; and the proposed loudness mapping model consumes substantially smaller amounts of memory. Aside from the applications in cochlear implants, this thesis describes a biologically plausible computational model of the auditory pathways to the superior colliculus based on current neurophysiological findings. The model encapsulates interaural time difference, interaural spectral difference, monaural pathway and auditory space map tuning in the inferior colliculus. A biologically plausible Hebbian-like learning rule is proposed for auditory space neural map tuning, and a reinforcement learning method is used for map alignment with other sensory space maps through activity independent cues. The validity of the proposed auditory pathway model has been verified by simulation using synthetic data. Further, a complete biologically inspired auditory simulation system is implemented in software. The system incorporates models of the external ear, the cochlea, as well as the proposed auditory pathway model. The proposed implementation can mimic the biological auditory sensory system to generate an auditory space map from 3—D sounds. A large amount of real 3-D sound signals including broadband White noise, click noise and speech are used in the simulation experiments. The efiect of the auditory space map developmental plasticity is examined by simulating early auditory space map formation and auditory space map alignment with a distorted visual sensory map. Detailed simulation methods, procedures and results are presented

Collective analog bioelectronic computation

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 677-710).In this thesis, I present two examples of fast-and-highly-parallel analog computation inspired by architectures in biology. The first example, an RF cochlea, maps the partial differential equations that describe fluid-membrane-hair-cell wave propagation in the biological cochlea to an equivalent inductor-capacitor-transistor integrated circuit. It allows ultra-broadband spectrum analysis of RF signals to be performed in a rapid low-power fashion, thus enabling applications for universal or software radio. The second example exploits detailed similarities between the equations that describe chemical-reaction dynamics and the equations that describe subthreshold current flow in transistors to create fast-and-highly-parallel integrated-circuit models of protein-protein and gene-protein networks inside a cell. Due to a natural mapping between the Poisson statistics of molecular flows in a chemical reaction and Poisson statistics of electronic current flow in a transistor, stochastic effects are automatically incorporated into the circuit architecture, allowing highly computationally intensive stochastic simulations of large-scale biochemical reaction networks to be performed rapidly. I show that the exponentially tapered transmission-line architecture of the mammalian cochlea performs constant-fractional-bandwidth spectrum analysis with O(N) expenditure of both analysis time and hardware, where N is the number of analyzed frequency bins. This is the best known performance of any spectrum-analysis architecture, including the constant-resolution Fast Fourier Transform (FFT), which scales as O(N logN), or a constant-fractional-bandwidth filterbank, which scales as O (N2).(cont.) The RF cochlea uses this bio-inspired architecture to perform real-time, on-chip spectrum analysis at radio frequencies. I demonstrate two cochlea chips, implemented in standard 0.13m CMOS technology, that decompose the RF spectrum from 600MHz to 8GHz into 50 log-spaced channels, consume < 300mW of power, and possess 70dB of dynamic range. The real-time spectrum analysis capabilities of my chips make them uniquely suitable for ultra-broadband universal or software radio receivers of the future. I show that the protein-protein and gene-protein chips that I have built are particularly suitable for simulation, parameter discovery and sensitivity analysis of interaction networks in cell biology, such as signaling, metabolic, and gene regulation pathways. Importantly, the chips carry out massively parallel computations, resulting in simulation times that are independent of model complexity, i.e., O(1). They also automatically model stochastic effects, which are of importance in many biological systems, but are numerically stiff and simulate slowly on digital computers. Currently, non-fundamental data-acquisition limitations show that my proof-of-concept chips simulate small-scale biochemical reaction networks at least 100 times faster than modern desktop machines. It should be possible to get 103 to 106 simulation speedups of genome-scale and organ-scale intracellular and extracellular biochemical reaction networks with improved versions of my chips. Such chips could be important both as analysis tools in systems biology and design tools in synthetic biology.by Soumyajit Mandal.Ph.D

A Switched-Capacitor degenerated, scalable gm - C filter-bank for acoustic front-ends

© 2016 IEEE. Filter-banks based on a gm-C topology are popular in acoustic sensor systems targeting spectral analysis. Their benefits lie in a very low power consumption and center-frequency scalability through gm-tuning to cover the audio frequency range. However the linear signal swing at the output of the filter is limited due to the inherent non-linearity of the input transistors in a differential pair. This work assesses the impact of noise and center-frequency specifications on the power consumption of 2 OTA base gm-C bandpass filters, both from a theoretical and practical point of view. Next, we introduce a novel scalable switched-capacitor based degeneration technique that enhances the linear signal swing at the filter output. Simulation results in 90nm CMOS demonstrate a power consumption of only 44nW for a bandpass filter with Q-factor of 1 with 63 dB dynamic range (< 2% THD) and a center-frequency of 100Hz. This scales to only 1. μW for a center-frequency at 3.2kHz. These power consumption numbers compare favorably with the state-of-the-art and enhance the Figure of Merit by more than 1.5X for a similar dynamic range.status: publishe

Low Power Memory/Memristor Devices and Systems

This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within