A Switched-Capacitor Band-Pass Biquad Filter Using a Simple Quasi-unity Gain Amplifier

Part 19: Electronics: AmplifiersInternational audienceThis paper presents a switched-capacitor (SC) band-pass biquad using a simple quasi-unity gain amplifier. In sub-nanometer CMOS technologies the intrinsic gain of the transistors is low; this increases the difficulty of designing high gain amplifiers. The proposed SC filter is based on the Sallen-Key biquad and it requires only a simple low gain amplifier. A differential filter circuit, including a suitable amplifier based on a fully-differential voltage-combiner is presented and analyzed. The correct functionality of this circuit is validated through electrical simulations of a second-order band-pass filter. These simulations show that, for a clock frequency of 100 MHz, the frequency response of the circuit is similar to the corresponding prototype filter

Analysis and Design Methodologies for Switched-Capacitor Filter Circuits in Advanced CMOS Technologies

Analog filters are an extremely important block in several electronic systems, such as RF transceivers, data acquisition channels, or sigma-delta modulators. They allow the suppression of unwanted frequencies bands in a signal, improving the system’s performance. These blocks are typically implemented using active RC filters, gm-C filters, or switched-capacitor (SC) filters. In modern deep-submicron CMOS technologies, the transistors intrinsic gain is small and has a large variability, making the design of moderate and high-gain amplifiers, used in the implementation of filter blocks, extremely difficult. To avoid this difficulty, in the case of SC filters, the opamp can be replaced with a voltage buffer or a low-gain amplifier (< 2), simplifying the amplifier’s design and making it easier to achieve higher bandwidths, for the same power. However, due to the loss of the virtual ground node, the circuit becomes sensitive to the effects of parasitic capacitances, which effect needs to be compensated during the design process. This thesis addresses the task of optimizing SC filters (mainly focused on implementations using low-gain amplifiers), helping designers with the complex task of designing high performance SC filters in advanced CMOS technologies. An efficient optimization methodology is introduced, based on hybrid cost functions (equation-based/simulation-based) and using genetic algorithms. The optimization software starts by using equations in the cost function to estimate the filter’s frequency response reducing computation time, when compared with the electrical simulation of the circuit’s impulse response. Using equations, the frequency response can be quickly computed (< 1 s), allowing the use of larger populations in the genetic algorithm (GA) to cover the entire design space. Once the specifications are met, the population size is reduced and the equation-based design is fine-tuned using the more computationally intensive, but more accurate, simulation-based cost function, allowing to accurately compensate the parasitic capacitances, which are harder to estimate using equations. With this hybrid approach, it is possible to obtain the final optimized design within a reasonable amount of computation time. Two methods are described for the estimation of the filter’s frequency response. The first method is hierarchical in nature where, in the first step, the frequency response is optimized using the circuit’s ideal transfer function. The following steps are used to optimize circuits, at transistor level, to replace the ideal blocks (amplifier and switches) used in the first step, while compensating the effects of the circuit’s parasitic capacitances in the ideal design. The second method uses a novel efficient numerical methodology to obtain the frequency response of SC filters, based on the circuit’s first-order differential equations. The methodology uses a non-hierarchical approach, where the non-ideal effects of the transistors (in the amplifier and in the switches) are taken into consideration, allowing the accurate computation of the frequency response, even in the case of incomplete settling in the SC branches. Several design and optimization examples are given to demonstrate the performance of the proposed methods. The prototypes of a second order programmable bandpass SC filter and a 50 Hz notch SC filter have been designed in UMC 130 nm CMOS technology and optimized using the proposed optimization software with a supply voltage of 0.9 V. The bandpass SC filter has a total power consumption of 249 uW. The filter’s central frequency can be tuned between 3.9 kHz and 7.1 kHz, the gain between -6.4 dB and 12.6 dB, and the quality factor between 0.9 and 6.9. Depending on the bit configuration, the circuit’s THD is between -54.7 dB and -61.7 dB. The 50 Hz notch SC filter has a total power consumption of 273 uW. The transient simulation of the circuit’s extracted view (C+CC) shows an attenuation of 52.3 dB in the 50 Hz interference and that the desired 5 kHz signal has a THD of -92.3 dB

A Signal Conditioner for Speech Processing

This thesis describes the design, implementation and testing of an analog signal conditioner for use in processing of speech signals. The signal conditioner provides gain and bandwidth control for the speech signal and also indicates the signal level. It is designed to be used in conjunction with a digital speech processor and has ports for a microphone or other signal source, an input signal monitoring device such as an oscilloscope, and interfaces to the digital speech processor. Signal bandwidth control is provided by a variable cutoff frequency lowpass switched capacitor filter, which is driven by a clock. In this thesis, the speech signal is examined and is related to the problem at hand. An overall description of the signal conditioner is then presented, emphasizing each of the signal conditioner is then presented, emphasizing each of the individual building blocks in the system. A description of switched capacitor filter theory and application follows, and signal conditioner system test results and conclusions are given. It was found that the system performance satisfied the desired specifications that were laid out when the system was first conceived

Low Voltage Low Power Analogue Circuits Design

Disertační práce je zaměřena na výzkum nejběžnějších metod, které se využívají při návrhu analogových obvodů s využití nízkonapěťových (LV) a nízkopříkonových (LP) struktur. Tyto LV LP obvody mohou být vytvořeny díky vyspělým technologiím nebo také využitím pokročilých technik návrhu. Disertační práce se zabývá právě pokročilými technikami návrhu, především pak nekonvenčními. Mezi tyto techniky patří využití prvků s řízeným substrátem (bulk-driven - BD), s plovoucím hradlem (floating-gate - FG), s kvazi plovoucím hradlem (quasi-floating-gate - QFG), s řízeným substrátem s plovoucím hradlem (bulk-driven floating-gate - BD-FG) a s řízeným substrátem s kvazi plovoucím hradlem (quasi-floating-gate - BD-QFG). Práce je také orientována na možné způsoby implementace známých a moderních aktivních prvků pracujících v napěťovém, proudovém nebo mix-módu. Mezi tyto prvky lze začlenit zesilovače typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za účelem potvrzení funkčnosti a chování výše zmíněných struktur a prvků byly vytvořeny příklady aplikací, které simulují usměrňovací a induktanční vlastnosti diody, dále pak filtry dolní propusti, pásmové propusti a také univerzální filtry. Všechny aktivní prvky a příklady aplikací byly ověřeny pomocí PSpice simulací s využitím parametrů technologie 0,18 m TSMC CMOS. Pro ilustraci přesného a účinného chování struktur je v disertační práci zahrnuto velké množství simulačních výsledků.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the non–conventional ones which are bulk–driven (BD), floating–gate (FG), quasi–floating–gate (QFG), bulk–driven floating–gate (BD–FG) and bulk–driven quasi–floating–gate (BD–QFG) techniques. The thesis also looks at ways of implementing structures of well–known and modern active elements operating in voltage–, current–, and mixed–mode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fully–differential second generation current conveyor (FB–CCII), fully–balanced differential difference amplifier (FB–DDA), voltage differencing transconductance amplifier (VDTA), current–controlled current differencing buffered amplifier (CC–CDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diode–less rectifier and inductance simulations, as well as low–pass, band–pass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.

Computer-Aided Design of Switched-Capacitor Filters

This thesis describes a series of computer methods for the design of switched-capacitor filters. Current software is greatly restricted in the types of transfer function that can be designed and in the range of filter structures by which they can be implemented. To solve the former problem, several new filter approximation algorithms are derived from Newton's method, yielding the Remez algortithm as a special case (confirming its convergency properties). Amplitude responses with arbitrary passband shaping and stopband notch positions are computed. Points of a specified degree of tangency to attenuation boundaries (touch points) can be placed in the response, whereby a family of transfer functions between Butterworth and elliptic can be derived, offering a continuous trade-off in group delay and passive sensitivity properties. The approximation algorithms have also been applied to arbitrary group delay correction by all-pass functions. Touch points form a direct link to an iterative passive ladder design method, which bypasses the need for Hurwitz factorisation. The combination of iterative and classical synthesis methods is suggested as the best compromise between accuracy and speed. It is shown that passive ladder prototypes of a minimum-node form can be efficiently simulated by SC networks without additional op-amps. A special technique is introduced for canonic realisation of SC ladder networks from transfer functions with finite transmission at high frequency, solving instability and synthesis difficulties. SC ladder structures are further simplified by synthesising the zeros at +/-2fs which are introduced into the transfer function by bilinear transformation. They cause cancellation of feedthrough branches and yield simplified LDI-type SC filter structures, although based solely on the bilinear transform. Matrix methods are used to design the SC filter simulations. They are shown to be a very convenient and flexible vehicle for computer processing of the linear equations involved in analogue filter design. A wide variety of filter structures can be expressed in a unified form. Scaling and analysis can readily be performed on the system matrices with great efficiency. Finally, the techniques are assembled in a filter compiler for SC filters called PANDDA. The application of the above techniques to practical design problems is then examined. Exact correction of sinc(x), LDI termination error, pre-filter and local loop telephone line weightings are illustrated. An optimisation algorithm is described, which uses the arbitrary passband weighting to predistort the transfer function for response distortions. Compensation of finite amplifier gain-bandwidth and switch resistance effects in SC filters is demonstrated. Two commercial filter specifications which pose major difficulties for traditional design methods are chosen as examples to illustrate PANDDA's full capabilities. Significant reductions in order and total area are achieved. Finally, test results of several SC filters designed using PANDDA for a dual-channel speech-processing ASIC are presented. The speed with which high-quality, standard SC filters can be produced is thus proven

Integrated realizations of reconfigurable low pass and band pass filters for wide band multi-mode receivers

With the explosive development of wireless communication systems the specifications of the supporting hardware platforms have become more and more demanding. According to the long term goals of the industry, future communications systems should integrate a wide variety of standards. This leads to the idea of software defined radio, implemented on fully reconfigurable hardware.Among other reconfigurable hardware blocks, suitable for the software radio concept, an outstanding importance belongs to the reconfigurable filters that are responsible for the selectivity of the system. The problematic of filtering is strictly connected to the architecture chosen for a multi-mode receiver realization. According to the chosen architecture, the filters can exhibit low pass or band pass frequency responses.The idea of reconfigurable frequency parameters has been introduced since the beginning of modern filtering applications due to the required precision of the frequency response. However, the reconfiguration of the parameters was usually done in a limited range around ideal values. The purpose of the presented research is to transform the classical filter structures with simple self-correction into fully reconfigurable filters over a wide range of frequencies. The ideal variation of the frequency parameters is continuous and consequently difficult to implement in real circuits. Therefore, it is usually sufficient to use a discrete programming template with reasonably small steps.There are several methods to implement variable frequency parameters. The most often used programming templates employ resistor and capacitor arrays, switched according to a given code. The low pass filter implementation proposed in this work uses a special switching template, optimized for a quasi-linear frequency variation over logarithmic axes. The template also includes the possibility to compensate errors caused by component tolerances and temperature. Another important topic concerns the implementation of programmable band pass filters, suitable for IF sampling receivers. The discussion is centered on the feasibility and the flexibility of different band pass filter architectures. Due to the high frequency requirements, the emphasis lays on filters that employ transconductance amplifiers and capacitors.Die rasch fortschreitende Entwicklung drahtloser Kommunikationssysteme führt zu immer anspruchsvolleren Spezifikationen der diese Systeme unterstützenden Hardwareplattformen. Zukünftige Kommunikationssysteme sollen übereinstimmend mit den längerfristigen Zielen der Industrie verschiedene Standards integrieren. Dies führt zu der Idee von vollständig rekonfigurierbarer Hardware, welche mittels Software gesteuert wird.Inmitten anderer rekonfigurierbarer Hardwareblöcke, die für das Software Radio Konzept geeignet sind, besitzen die steuerbaren Filter, welche wesentlichen Einfluss auf die Selektivität des Systems haben, eine enorme Bedeutung. Die Filterproblematik ist eng mit der gewählten Architektur der standardübergreifenden Empfängerrealisierung verknüpft. Die Filter können entsprechend der ausgesuchten Architektur Tiefpass- oder Bandpasscharakter annehmen.Die Idee rekonfigurierbarer Frequenzparameter wurde bereits mit Beginn moderner Filteranwendungen auf Grund geforderter Frequenzganggenauigkeit umgesetzt. Jedoch wurde die Parameterrekonfiguration üblicherweise nur in einem begrenzten Bereich um die Idealwerte herum vorgenommen. Das Ziel der vorgestellten Forschungsarbeit ist es, diese klassischen Filterstrukturen mit einfacher Selbstkorrektur in über große Frequenzbereiche voll rekonfigurierbare Filter zu transformieren. Idealerweise werden die Frequenzparameter kontinuierlich variiert weswegen sich die Implementierung in reellen Schaltkreisen als schwierig erweist. Deshalb ist es üblicherweise ausreichend, ein diskretes Steuerschema mit kleinen Schrittweiten zu verwenden.Es gibt verschiedene Methoden, variable Frequenzparameter zu implementieren. Die meisten Schemata verwenden Widerstands- und Kondensatorfelder, die entsprechend eines Kodes geschaltet werden. Die in dieser Arbeit vorgestellte Implementierung eines Tiefpassfilters nutzt ein spezielles Umschaltschema, welches für die quasi-lineare Frequenzvariation bei Darstellung über logarithmischen Axen optimiert wurde. Es beinhaltet weiterhin die Möglichkeit, Fehler zu kompensieren, die durch Bauelementtoleranzen und Temperaturschwankungen hervorgerufen werden.Ein weiteres interessantes Thema betrifft die Implementierung steuerbarer Bandpassfilter, die für Empfänger mit Zwischenfrequenzabtastung geeignet sind. Die Betrachtung beschränkt sich hierbei auf die Durchführbarkeit und Flexibilität verschiedener Bandpassfilterarchitekturen. Auf Grund hoher Frequenzanforderungen liegt der Schwerpunkt auf Filtern, die auf Transkonduktanzverstärkern und Kondensatoren basieren

Analogue filter networks: developments in theory, design and analyses

Not availabl

Baseband analog circuits in deep-submicron cmos technologies targeted for mobile multimedia

Three main analog circuit building blocks that are important for a mixed-signal system are investigated in this work. New building blocks with emphasis on power efficiency and compatibility with deep-submicron technology are proposed and experimental results from prototype integrated circuits are presented. Firstly, a 1.1GHz, 5th order, active-LC, Butterworth wideband equalizer that controls inter-symbol interference and provides anti-alias filtering for the subsequent analog to digital converter is presented. The equalizer design is based on a new series LC resonator biquad whose power efficiency is analytically shown to be better than a conventional Gm-C biquad. A prototype equalizer is fabricated in a standard 0.18μm CMOS technology. It is experimentally verified to achieve an equalization gain programmable over a 0-23dB range, 47dB SNR and -48dB IM3 while consuming 72mW of power. This corresponds to more than 7 times improvement in power efficiency over conventional Gm-C equalizers. Secondly, a load capacitance aware compensation for 3-stage amplifiers is presented. A class-AB 16W headphone driver designed using this scheme in 130nm technology is experimentally shown to handle 1pF to 22nF capacitive load while consuming as low as 1.2mW of quiescent power. It can deliver a maximum RMS power of 20mW to the load with -84.8dB THD and 92dB peak SNR, and it occupies a small area of 0.1mm2. The power consumption is reduced by about 10 times compared to drivers that can support such a wide range of capacitive loads. Thirdly, a novel approach to design of ADC in deep-submicron technology is described. The presented technique enables the usage of time-to-digital converter (TDC) in a delta-sigma modulator in a manner that takes advantage of its high timing precision while noise-shaping the error due to its limited time resolution. A prototype ADC designed based on this deep-submicron technology friendly architecture was fabricated in a 65nm digital CMOS technology. The ADC is experimentally shown to achieve 68dB dynamic range in 20MHz signal bandwidth while consuming 10.5mW of power. It is projected to reduce power and improve speed with technology scaling

Analogue micropower FET techniques review

A detailed introduction to published analogue circuit design techniques using Si and Si/SiGe FET devices for very low-power applications is presented in this review. The topics discussed include sub-threshold operation in FET devices, micro-current mirrors and cascode techniques, voltage level-shifting and class-AB operation, the bulk-drive approach, the floating-gate method, micropower transconductance-capacitance and log-domain filters and strained-channel FET technologies