7,811 research outputs found
Sparks of GPTs in Edge Intelligence for Metaverse: Caching and Inference for Mobile AIGC Services
Aiming at achieving artificial general intelligence (AGI) for Metaverse,
pretrained foundation models (PFMs), e.g., generative pretrained transformers
(GPTs), can effectively provide various AI services, such as autonomous
driving, digital twins, and AI-generated content (AIGC) for extended reality.
With the advantages of low latency and privacy-preserving, serving PFMs of
mobile AI services in edge intelligence is a viable solution for caching and
executing PFMs on edge servers with limited computing resources and GPU memory.
However, PFMs typically consist of billions of parameters that are computation
and memory-intensive for edge servers during loading and execution. In this
article, we investigate edge PFM serving problems for mobile AIGC services of
Metaverse. First, we introduce the fundamentals of PFMs and discuss their
characteristic fine-tuning and inference methods in edge intelligence. Then, we
propose a novel framework of joint model caching and inference for managing
models and allocating resources to satisfy users' requests efficiently.
Furthermore, considering the in-context learning ability of PFMs, we propose a
new metric to evaluate the freshness and relevance between examples in
demonstrations and executing tasks, namely the Age of Context (AoC). Finally,
we propose a least context algorithm for managing cached models at edge servers
by balancing the tradeoff among latency, energy consumption, and accuracy
Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review
The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER
Performance Analysis of Distributed Cache Invalidation Method in Mobile Ad hoc Networks using AODV and AOMDV Routing Protocols
Mobile Ad hoc Networks (MANETs) is an active wireless network that can be formed without any existing permanent framework networks. Mobile Ad hoc Networks is an independent structure of mobile nodes communicated with wireless channels. Distributed cache invalidation method is performed among intermediate routing mobile nodes. In MANETs routing protocols are provided desirable route establishments of the mobile nodes. Ad hoc On-demand distance vector routing protocol (AODV) was well known single route protocol , Ad hoc On-demand Multipath Distance Vector routing protocol (AOMDV) is extends the AODV protocol with multipath. These results are carried out in network simulator version2 (NS2), the performance is analyzed and compared between AODV and AOMDV routing protocols
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