Architektur moderner RISC-Mikroprozessoren

Seit der Entwicklung des ersten Mikroprozessors vor rund 25 Jahren konnte die Prozessorleistung kontinuierlich um jährlich 50 % verbessert werden. Diese Leistungsverbesserung ist im wesentlichen den Fortschritten der Halbleiterindustrie zu verdanken, welche den Entwicklern von integrierten Schaltungen einerseits immer schnellere Transistoren und andererseits eine immer grössere Anzahl Transistoren auf einem Chip zur Verfügung stellt. Damit kann die Prozessorleistung erhöht werden, ohne dass Änderungen an der Prozessororganisation nötig sind: die höhere Schaltgeschwindigkeit erlaubt es, Instruktionen schneller auszuführen, und die höhere Integrationsdichte kann dazu benutzt werden, breitere Datenpfade zu realisieren und damit breitere Operandenworte zu verarbeiten. Daneben sind aber auch architektonische Erweiterungen wesentlich mitverantwortlich an der Erhöhung der Rechenleistung. Die beiden wichtigsten Techniken, um die Arbeitsgeschwindigkeit von Mikroprozessoren weiter zu erhöhen, sind die Pipelineverarbeitung und die Verwendung von Cachespeichern. Die Pipelineverarbeitung erlaubt es, mehrere Operationen parallel auszuführen, während Cachespeicher einen schnelleren Zugriff auf Operationen und Operanden ermöglichen. In diesem Artikel werden die erwähnten Techniken besprochen und deren Anwendung in modernen RISC-Mikroprozessoren aufgezeigt

Improving GPU SIMD Control Flow Efficiency via Hybrid Warp Size Mechanism

High single instruction multiple data (SIMD) efficiency and low power consumption have made graphic processing units (GPUs) an ideal platform for many complex computational applications. Thousands of threads can be created by programmers and grouped into fixed-size SIMD batches, known as warps. High throughput is then achieved by concurrently executing such warps with minimal control overhead. However, if a branch instruction occurs, which assigns different paths to different threads, this warp will be broken into multiple warps that have to be executed serially, consequently reducing the efficiency advantage of SIMD. In this thesis, the contemporary fixed-size warp design is abandoned and a hybrid warp size (HWS) mechanism is proposed. Mixed-size warps are generated according to HWS and are scheduled and issued flexibly. Once a branch divergence occurs, split warps are squeezed according to the proposed algorithm, and warp sizes are downscaled wherever applicable. Based on updated warp sizes, warp schedulers calculate the number of cycles the current warp needs and issue the next warp accordingly. As a result, hybrid warps are pushed into pipelines as soon as possible and more pipeline stages are overlapped. The simulation results show that this mechanism yields an average speedup of 1.20 over the baseline architecture for a wide variety of general purpose GPU applications. This work also integrates HWS with dynamic warp formation (DWF), which is a well-known branch handling mechanism aimed at improving SIMD utilization by forming new warps out of split warps in real time. The warp forming policy is modified to better tolerate warp conflicts. Also, squeeze operations are added before a warp merges with other warps. The simulation shows that the combination of DWF and HWS generates an average speedup of 1.27 over the DWF-only platform for the same set of GPU benchmarks

Exploiting Fine-Grain Concurrency Analytical Insights in Superscalar Processor Design

This dissertation develops analytical models to provide insight into various design issues associated with superscalar-type processors, i.e., the processors capable of executing multiple instructions per cycle. A survey of the existing machines and literature has been completed with a proposed classification of various approaches for exploiting fine-grain concurrency. Optimization of a single pipeline is discussed based on an analytical model. The model-predicted performance curves are found to be in close proximity to published results using simulation techniques. A model is also developed for comparing different branch strategies for single-pipeline processors in terms of their effectiveness in reducing branch delay. The additional instruction fetch traffic generated by certain branch strategies is also studied and is shown to be a useful criterion for choosing between equally well performing strategies. Next, processors with multiple pipelines are modelled to study the tradeoffs associated with deeper pipelines versus multiple pipelines. The model developed can reveal the cause of performance bottleneck: insufficient resources to exploit discovered parallelism, insufficient instruction stream parallelism, or insufficient scope of concurrency detection. The cost associated with speculative (i.e., beyond basic block) execution is examined via probability distributions that characterize the inherent parallelism in the instruction stream. The throughput prediction of the analytic model is shown, using a variety of benchmarks, to be close to the measured static throughput of the compiler output, under resource and scope constraints. Further experiments provide misprediction delay estimates for these benchmarks under scope constraints, assuming beyond-basic-block, out-of-order execution and run-time scheduling. These results were derived using traces generated by the Multiflow TRACE SCHEDULING™(*) compacting C and FORTRAN 77 compilers. A simplified extension to the model to include multiprocessors is also proposed. The extended model is used to analyze combined systems, such as superpipelined multiprocessors and superscalar multiprocessors, both with shared memory. It is shown that the number of pipelines (or processors) at which the maximum throughput is obtained is increasingly sensitive to the ratio of memory access time to network access delay, as memory access time increases. Further, as a function of inter-iteration dependency distance, optimum throughput is shown to vary nonlinearly, whereas the corresponding Optimum number of processors varies linearly. The predictions from the analytical model agree with published results based on simulations. (*)TRACE SCHEDULING is a trademark of Multiflow Computer, Inc

Beehive: an FPGA-based multiprocessor architecture

In recent years, to accomplish with the Moore's law hardware and software designers are tending progressively to focus their efforts on exploiting instruction-level parallelism. Software simulation has been essential for studying computer architecture because of its flexibility and low cost. However, users of software simulators must choose between high performance and high fidelity emulation. This project presents an FPGA-based multiprocessor architecture to speed up multiprocessor architecture research and ease parallel software simulation

Simultaneous multithreading: Operating system perspective

Developing CPU architecture is a very complicated, iterative process that requires significant time and money investments. The motivation for this work is to find ways to decreases the amount of time and money needed for the development of hardware architectures. The main problem is that it is very difficult to determine the performance of the architecture, since it is impossible to take any performance measurements untill upon completion of the development process. Consecutively, it is impossible to improve the performance of the product or to predict the influence of different parts of the architecture on the architecture\u27s overall performance. Another problem is that this type of development does not allow for the developed system to be reconfigured or altered without complete re-development. . The solution to the problems mentioned above is the software simulators that allow researching the architecture before even starting to cut the silicon.. Simultaneous multithreading (SMT) is a modern approach to CPU design. This technique increases the system throughput by decreasing both total instruction delay and stall times of the CPU. The gain in performance of a typical SMT processor is achieved by allowing the instructions from several threads to be fetched by an operating system into the CPU simultaneously. In order to function successfully the CPU needs software support. In modern computer systems the influence of an operating system on overall system performance can no longer be ignored. It is important to understand that the union of the CPU and the supporting operating system and their interdependency determines the overall performance of any computer system. In the system that has been implemented on hardware level such analysis is impossible, since the hardware system is neither flexible nor configurable. However, in the SMT architecture, the system is capable of performing some useful work even if a task has generated an error. A wide range of simulators is described in the literature, and a lot of them are publicly accessible. The main goal of this work is to modify an existing SEVIOS/Topsy simulator to achieve a simple, configurable, publicly accessible SMT SEVIOS/Topsy simulator that must also include an SMT Topsy.. The simulator should demonstrate the fetching process of the SMT MIPS, as well as scheduling aspects of the CPU and the operating system integrated environment.. This work covers a broad range of aspects, among which are: 1) Completion of SMT MIPS and SMT Topsy specifications; 2) Integration of MXS into SIMOS/Topsy; 3) Modifications to the fetching unit of MXS that allow to support SMT; 4) Addition of SMT support to Topsy;; This work uses Topsy/R4000 simulator developed at Swiss Federal Institute of Technology, and the MXS (R10000) part of the SimOS simulator developed at Stanford University. Development process utilizes C high-level language, Intel and MIPS assembly languages. The result of this work is a development of a complete computer system software simulator. The simulator allows taking performance measurements and reconfiguration of SMT Topsy and the fetching unit of the SMT MXS. The simulator is modular: that is any of its parts can be substituted with other parts that perform similar functionality. It also means that the whole simulator can be integrated into a larger scale simulation project. The development of this simulator significantly decreases the amount of time and money needed for the development of hardware architectures and provides new ways in researching the influence of an operating system on the performance of the computer system as a whole

Beehive: an FPGA-based multiprocessor architecture

In recent years, to accomplish with the Moore's law hardware and software designers are tending progressively to focus their efforts on exploiting instruction-level parallelism. Software simulation has been essential for studying computer architecture because of its flexibility and low cost. However, users of software simulators must choose between high performance and high fidelity emulation. This project presents an FPGA-based multiprocessor architecture to speed up multiprocessor architecture research and ease parallel software simulation

Embedded Processor Selection/Performance Estimation using FPGA-based Profiling

In embedded systems, modeling the performance of the candidate processor architectures is very important to enable the designer to estimate the capability of each architecture against the target application. Considering the large number of available embedded processors, the need has increased for building an infrastructure by which it is possible to estimate the performance of a given application on a given processor with a minimum of time and resources. This dissertation presents a framework that employs the softcore MicroBlaze processor as a reference architecture where FPGA-based profiling is implemented to extract the functional statistics that characterize the target application. Linear regression analysis is implemented for mapping the functional statistics of the target application to the performance of the candidate processor architecture. Hence, this approach does not require running the target application on each candidate processor; instead, it is run only on the reference processor which allows testing many processor architectures in very short time