DESIGN OF LOW-POWER LOW-VOLTAGE SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS

Ph.DDOCTOR OF PHILOSOPH

Systematic Design Methodology for Successive – Approximation ADCs

Successive – Approximation ADCs are widely used in ultra – low – power applications. This paper describes a systematic design procedure for designing Successive – Approximation ADCs for biomedical sensor nodes. The proposed scheme is adopted in the design of a 12 bit 1 kS/s ADC. Implemented in 65 nm CMOS, the ADC consumes 354 nW at a sampling rate of 1 kS/s operating with 1.2 supply voltage. The achieved ENOB is 11.6, corresponding to a FoM of 114 fJ/conversion – step

Using behavioral modeling and simulation for learning communication circuits and systems

Comunicación presentada al "Global Engineering Education Conference (EDUCON)" celebrado en Marrakech (Marruecos) del 17 al 20 de Abril del 2012.This paper analyzes the use of behavioral simulation techniques to enhance the teaching-learning process in electrical engineering courses, specifically those dealing with circuits for communication systems. The method - which can be applied to both undergraduate and master courses - allows students to better understand complex circuit- and device-level phenomena, by describing them at a higher abstraction level. As a demonstration vehicle of the presented methodology, two examples are considered in this work: an analog front-end of a direct-conversion digital radio receiver and a ΣΔ modulator. In both cases, behavioral models of the different subcircuits have been implemented in MATLAB/SIMULINK and used by the students enrolled in two different courses: an undergraduate course and a master course. The results presented in this paper reveal that students become highly motivated and satisfied with the course contents and the proposed simulation-based learning methodology.This work has been supported in part by the Spanish Ministry of Science and Innovation (with support from the European Regional Development Fund) under contracts TEC2007-67247-C02-01/MIC, TEC2010-14825/MIC, in part by the Consejería de Innovación, Ciencia y Empresa, under contract TIC-2532 and in part by the I Plan Propio de Docencia de la U. de Sevilla, LabCMA2010 project.Peer Reviewe

A Temperature – and Supply- Variation Robust 2nd-Order Sigma-Delta Modulation for Capacitive Sensing

Capacitance to digital converter, VCO quantizer, Sigma-Delta modulation, Supply variation, temperature variationIn this paper, I proposed a temperature- and supply variation robust 2nd-order sigma-delta modulation circuit for capacitive sensing. Capacitive sensing by conventional circuits is basically supply sensitive. Capacitance is sensed by reading the charge that is equal to the difference between the capacitance value of the capacitor and the capacitor to be sensed. In this method, the amount of charge is dependent on the supply, so it is insensitive to supply variation. In this paper, the capacitance is read by using the time determined by the discharge characteristics when a capacitor called T0V meets the resistance component. The charge accumulated in the capacitor is certainly influenced by the supply value, but capacitive sensing is performed using the characteristic that the time taken to discharge the charge to zero is always constant. In the process, VCO (Voltage-Controlled-Oscillator) based ADC (Analog-to-Digital Converter) was used to increase the resolution by utilizing the noise shaping effect of sigma-delta ADC. In the process, the resistor is switched to a switched capacitor to obtain robust characteristics against temperature variations. Unlike resistance whose values change with temperature, capacitance are relatively robust to temperature effects. By using the characteristics, a circuit having robust characteristics in temperature variation as well as robust in supply variation.openAbstract i List of contents iii List of figures iv List of figures v Ⅰ. Introduction 1.1 Motivation and Objective 1 1.2 Theses outline 3 ⅠI. Supply- Variation Robust 2nd-Order Sigma-Delta Modulation 2.1 Supply Independent Technique 4 2.2 Injection Locking Current Controlled Oscillator 8 2.3 VCO Based ADC 13 2.4 Full Architecture 16 2.4.1 Control Block 19 2.4.2 Block Diagram 21 2.5 Schematic and Layout 23 III. Temperature- and Supply- Variation Robust 2nd-Order Sigma-Delta Modulation 3.1 Switched Capacitor DAC 31 3.2 Switched Capacitor Clock Generator 36 3.3 Control Block 38 3.4 Schematic 39 IV. Simulation and Measurement Result 4.1 Resistor DAC Circuit 42 4.1.1 Measurement Result 42 4.2 Switched Capacitor DAC Circuit 45 4.2.1 Simulation Result 45 V. Conclusion본 논문은 전원변화 및 온도변화에도 안정적으로 정전용량을 읽어낼 수 있는 2차 시그마-델타 변조기 회로이다. 커패시터의 방전 시간이 전원의 영향이 아닌 정전용량과 저항 값에만 영향을 받는다는 점을 이용하여 회로를 구성하였다. 또한 저항이 온도변화에 따라서 일정한 값을 유지하기 힘들다는 점을 보완하기위해 switched capacitor 기법을 사용하였다. 커패시터는 저항에 비해 상대적으로 온도변화에도 정전용량을 안정적인 값으로 유지할 수 있다. 이 점을 이용하여 전원변화뿐 만이 아닌 온도변화에도 강인한 특성을 가질 수 있게 된다. 또 전압제어발진기를 활용한 아날로그-디지털 변환기법도 사용되었다. 전압제어발진기에 ‘전압제어발진기 기반 양자화기’라는 양자화를 할 수 있는 회로를 연결하여 동작이 진행된다. 이 기법을 사용하게 되면 양자화오류의 성분들이 백색잡음처럼 모든 주파수대역에 걸쳐서 골고루 존재하는 것이 아닌, 고주파 쪽을 향해 20dB의 기울기를 가지며 상승하는 형태로 나타난다. 최종적인 전체 루프의 특성을 확인하면 40dB의 기울기를 가지며 상승하는 형태를 갖는다. 이 특성을 통하여 동작 대역폭이 아닌 더 고주파 영역으로 양자화 오류 성분들을 밀어낼 수 있다는 장점이 있다. 그 결과, SNR이 상승하게 되어 최종적으로 정전용량을 읽어낼 수 있는 분해능 성능이 좋아지게 된다.MasterdCollectio

Study of a Time Assisted SAR ADC

The demand for low power systems has been increasing in recent years and Analogto- Digital Converters (ADCs) are key blocks of many of these systems as they convert a physical quantity into the digital domain so that this information can be further processed or stored using digital techniques. Data Converters based on Charge Redistribution using of Successive Approximation Registers (SAR) are becoming one of the most popular ADC architectures for moderate speed, medium resolution and low power applications. Due to their low analog complexity SAR ADCs benefit from technology scaling. However, this scaling often comes with a supply voltage reduction and the noise levels do not decrease at the same rate, which translates into a performance decrease. Therefore, new opportunities emerge to explore other physical quantities such as time, frequency, phase or charge in the circuit. This thesis focuses on studying how the time domain information can be used to increase the performance of SAR ADCs. To do so, a new SAR ADC architecture is proposed in which a Time-to-Digital Converter (TDC) is used to convert the time domain information, provided by the comparator, into the digital domain. This new architecture was modelled in MATLAB as a 12 bit TDC assisted SAR ADC, using information from electrical simulations of the comparator and the TDC, designed in Cadence in 65 nm ST Microelectronics CMOS technology. Simulation results demonstrated that, to achieve a better performance when compared to more traditional SAR structures, the TDC energy and latency should be minimized. Another limiting factor was the large voltage range in which only 1 bit could be extracted from the time-to-voltage conversion by the TDC due to the comparator’s fast response in this range. The proposed architecture was also extended to incorporate a Bypass Window in the time domain, which allowed to substantially decrease the number of clock cycles necessary to solve the 12 bits of the ADC