Statistical modelling of nano CMOS transistors with surface potential compact model PSP

The development of a statistical compact model strategy for nano-scale CMOS transistors is presented in this thesis. Statistical variability which arises from the discreteness of charge and granularity of matter plays an important role in scaling of nano CMOS transistors especially in sub 50nm technology nodes. In order to achieve reasonable performance and yield in contemporary CMOS designs, the statistical variability that affects the circuit/system performance and yield must be accurately represented by the industry standard compact models. As a starting point, predictive 3D simulation of an ensemble of 1000 microscopically different 35nm gate length transistors is carried out to characterize the impact of statistical variability on the device characteristics. PSP, an advanced surface potential compact model that is selected as the next generation industry standard compact model, is targeted in this study. There are two challenges in development of a statistical compact model strategy. The first challenge is related to the selection of a small subset of statistical compact model parameters from the large number of compact model parameters. We propose a strategy to select 7 parameters from PSP to capture the impact of statistical variability on current-voltage characteristics. These 7 parameters are used in statistical parameter extraction with an average RMS error of less than 2.5% crossing the whole operation region of the simulated transistors. Moreover, the accuracy of statistical compact model extraction strategy in reproducing the MOSFET electrical figures of merit is studied in detail. The results of the statistical compact model extraction are used for statistical circuit simulation of a CMOS inverter under different input-output conditions and different number of statistical parameters. The second challenge in the development of statistical compact model strategy is associated with statistical generation of parameters preserving the distribution and correlation of the directly extracted parameters. By using advanced statistical methods such as principal component analysis and nonlinear power method, the accuracy of parameter generation is evaluated and compared to directly extracted parameter sets. Finally, an extension of the PSP statistical compact model strategy to different channel width/length devices is presented. The statistical trends of parameters and figures of merit versus channel width/length are characterized

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface

Multigate MOSFETs for digital performance and high linearity, and their fabrication techniques

The aggressive downscaling of complementary metal–oxide–semiconductor (CMOS) technology is facing great challenges to overcome severe short-channel effects. Multigate MOSFETs are one of the most promising candidates for scaling beyond Si CMOS, due to better electrostatic control as compared to conventional planar MOSFETs. Conventional dry etching-induced surface damage is one of the main sources of performance degradation for multigate transistors, especially for III-V high mobility materials. It is also challenging to increase the fin aspect ratio by dry etching because of the non-ideal anisotropic etching profile. Here, we report a novel method, inverse metal-assisted chemical etching (i-MacEtch), in lieu of conventional RIE etching, for 3D fin channel formation. InP junctionless FinFETs with record high-aspect-ratio (~ 50:1) fins are demonstrated by this method for the first time. The i-MacEtch process flow eliminates dry-etching-induced plasma damage, high energy ion implantation damage, and high temperature annealing, allowing for the fabrication of InP fin channels with atomically smooth sidewalls. The sidewall features resulting from this unique and simplified process ensure high interface quality between high-k dielectric layer and InP fin channel. Experimental and theoretical analyses show that high-aspect-ratio FinFETs, which could deliver more current per area under much relaxed horizontal geometry requirements, are promising in pushing the technology node ahead where conventional scaling has met its physical limits. The performance of the FinFET was further investigated through numerical simulation. A new kind of FinFET with asymmetric gate and source/drain contacts has been proposed and simulated. By benchmarking with conventional symmetric FinFET, better short-channel behavior with much higher current density is confirmed. The design guidelines are provided. The overall circuit delay can be minimized by optimizing gate lengths according to different local parasites among circuits in interconnection-delay-dominated SoC applications. Continued transistor scaling requires even stronger gate electrostatic control over the channel. The ultimate scaling structure would be gate-all-around nanowire MOSFETs. We demonstrate III-V junctionless gate-all-around (GAA) nanowire (NW) MOSFETs for the first time. For the first time, source/drain (S/D) resistance and thermal budget are minimized by regrowth using metalorganic chemical vapor deposition (MOCVD) in III-V MOSFETs. The fabricated short-channel (Lg=80 nm) GaAs GAA NWFETs with extremely narrow nanowire width (WNW= 9 nm) show excellent transconductance (gm) linearity at biases (300 mV), characterized by the high third intercept point (2.6 dBm). The high linearity is especially important for low power applications because it is insensitive to bias conditions

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Experimental studies on germanium-tin p-channel tunneling field effect transistors

Recent years have shown a growing interest in device concepts based on quantum mechanical tunneling. The tunneling field effect transistor (TFET) is a device that competes directly with the metal-oxide-semiconductor field effect transistor (MOSFET) in terms of speed, power and area. The drive current injection mechanism in TFETs is a band-to-band tunneling (BTBT) current and the promise of the TFET lies in its steep subtreshold current-voltage (I-V) characteristics, which is not restricted by the MOSFET’s 60 mV/dec limit at room temperature. TFETs could perform better at low supply voltages, but improvement of the drive current is necessary to outperform the MOSFET. In this work different device tuning strategies for the p-channel germanium (Ge) TFET are studied. Modifications involving the semiconductor material and doping profiles are investigated with the aim of increasing the tunneling probability and achieving high drive currents. This investigation has been conducted through designing, fabricating and characterizing the vertical TFET structures. Vertical semiconductor structures were grown by means of molecular beam epitaxy (MBE), and the vertical devices were fabricated using a gate-all-around (GAA) geometry fabrication process. It is shown that the drive current (ION) can be effectively increased by the introduction of germanium-tin (GeSn) in the channel. A successive increase in ION is seen when increasing the tin (Sn)-content, x, in a germanium-tin (Ge1-xSnx) channel from x = 0 % to x = 2 % and x = 4 %. This is due to the lowering of the bandgap, which effectively increases the tunneling probability. Furthermore, it is found that when Ge0.96Sn0.04 is confined within a 10 nm delta-layer, TFET device performance can be tuned by shifting the position of this layer at the source-channel interface. A high ION is achieved when this layer is completely inside the channel, while the leakage current (IOFF) is reduced when this layer is shifted from the channel and into the source. A complicating factor with incorporating Ge1-xSnx in the p-channel Ge TFETs is found to be the difficulty of maintaining a high epitaxial quality when increasing the Sn content. Together with the lowering of the bandgap, this is shown to degrade the IOFF and subthreshold swing (SS) of the device through increased Shockley-Read-Hall (SRH) generation and trap-assisted tunneling (TAT) currents. This further calls into question the feasibility of achieving acceptable performance with GeSn as channel material. Based on the results, some device performance strategies are discussed. Varying the source doping concentration in p-channel Ge TFETs with gate-source overlap is found to mainly influence the subthreshold characteristics of the devices. Steeper subthreshold characteristics is found with increasing source doping concentration. This correlation is believed to be a result of TAT in the source-gate overlap region. Contrary to results from published simulation studies, no effect of varying the source doping concentration on ION could be distinguished for the doping levels investigated. A MBE pre-buildup technique of antimony (Sb) is investigated as a means to achieve steep source doping profiles in vertical p-channel Ge TFETs. It is seen that for a Sb pre-buildup concentration of 1/20 monolayer (ML), both ION and SS is improved. This is explained by that the extent of the tunneling barrier into the source region is reduced, leading to an increase of the tunneling probability and improvement of the band pass filtering. The boost in ION is small, but the pre-buildup technique imposes no extra load onto the TFET fabrication process and can easily be combined with other strategies for boosting the drive current for TFETs. The results also suggests that an optimal pre-buildup doping exists. In this work also the aluminum oxide (Al2O3), which is used as gate oxide, and the Ge/Al2O3/Al system is studied. A germanium oxide (GeOx)-passivation achieved through post-plasma oxidation and a sulfur (S)-passivation achieved through an aqueous Ammonium sulfite solution treatment, are both investigated through the fabrication and electrical characterization of MOS-capacitors. For the sample passivated with GeOx, a hysteresis and a shift in the flatband voltage is explained by acceptor traps in the oxide. A general parallel shift of the capacitance-voltage (C-V)-curve towards positive gate voltages indicates fixed negative charges and an O-rich Al2O3. It is suggested that these O-rich regions could be induced by the post plasma oxidation treatment. Temperature dependent current-voltage (I-V)-characteristics indicate a Schottky emission process as the main transport mechanism through the oxide at low electric fields. The effect of S-passivation of the Ge surface is seen to reduce both the C-V hysteresis and the leakage current in the low E-field region. The measured oxide capacitances also reveal that this does not come at the expense of a thicker equivalent oxide thickness (EOT)

Ferroelectric Field Effect Transistor for Memory and Switch Applications

Silicon technology has advanced at exponential rates both in performances and productivity through the past four decades. However the limit of CMOS technology seems to be closer and closer and in the future we might see an increasing number of hybrid approaches where other technologies add to the CMOS performance, while maintaining a back-bone of CMOS logic. Ferro-electricity in ultra-thin films has been investigated as a credible candidate for nonvolatile memory thanks to the bistability of polarization. 1 transistor (1T) ferroelectric memory cells have been proposed and experimentally studied in order to reduce the size of 1T-1C (1Transistor-1Capacitor) design with consequent advantages in terms of size, read-out operation and costs. More recently ferroelectrics have been proposed by Salahuddin and Datta as dielectric materials in order to lower the 60mV/dec limit of the subthreshold swing (SS) in silicon Metal Oxide Semiconductor Field Effect Transistors, MOSFETs. The objective of this thesis is to study the ferroelectric transistor performance for both memory and switch application. For this purpose different Ferroelectric Field Effect Transistors, Fe-FETs, structures have been designed, fabricated and characterized. An organic ferroelectric polymer, vinylidene fluoride trifluorethylene, P(VDF-TrFE), of 100nm and 40nm thickness has been successfully integrated into the gate stack of bulk and SOI MOSFET and, later, on a Tunnel FET, TFET, structure. The 1T ferroelectric FET memory cells have shown a programming time in the order of ms at 9V as programming voltage. The retention of a few seconds, however, is the main limiting factor for the usage of this device for NV-memory applications. The retention failure mechanisms have been studied and investigated for future improvement. For the first time this work experimentally demonstrates that a subthreshold swing lower than 60mv/dec can be achieved in a ferroelectric transistor thanks to the voltage amplification arising from the ferroelectric material. This unique finding has been first measured in a 40nm P(VDF-TrFE)/10nm SiO2 gate stack MOSFET and then, confirmed, in a 100nm P(VDF-TrFE)/10nm SiO2 gate MOSFET with an intermediate contact between the two dielectrics. This internal node contact allows the study of the voltage amplification due to the ferroelectric material. Finally a temperature study of the performance of a ferroelectric Fully Depleted Silicon on Insulator, FD SOI, transistor has been done. A model based on Landau's theory has been carried out and it has been experimentally validated for both the subthreshold and the strong inversion regions. It has been demonstrated for the first time that, because of the divergence of the ferroelectric permittivity at the Curie temperature, Tc, a ferroelectric transistor has a maximum and a minimum, respectively of its transconductance and subthreshold swing, at Tc

Integrated Circuits/Microchips

With the world marching inexorably towards the fourth industrial revolution (IR 4.0), one is now embracing lives with artificial intelligence (AI), the Internet of Things (IoTs), virtual reality (VR) and 5G technology. Wherever we are, whatever we are doing, there are electronic devices that we rely indispensably on. While some of these technologies, such as those fueled with smart, autonomous systems, are seemingly precocious; others have existed for quite a while. These devices range from simple home appliances, entertainment media to complex aeronautical instruments. Clearly, the daily lives of mankind today are interwoven seamlessly with electronics. Surprising as it may seem, the cornerstone that empowers these electronic devices is nothing more than a mere diminutive semiconductor cube block. More colloquially referred to as the Very-Large-Scale-Integration (VLSI) chip or an integrated circuit (IC) chip or simply a microchip, this semiconductor cube block, approximately the size of a grain of rice, is composed of millions to billions of transistors. The transistors are interconnected in such a way that allows electrical circuitries for certain applications to be realized. Some of these chips serve specific permanent applications and are known as Application Specific Integrated Circuits (ASICS); while, others are computing processors which could be programmed for diverse applications. The computer processor, together with its supporting hardware and user interfaces, is known as an embedded system.In this book, a variety of topics related to microchips are extensively illustrated. The topics encompass the physics of the microchip device, as well as its design methods and applications

Characterisation and noise analysis of high Ge content p-channel SiGe MOSFETs fabricated using virtual substrates

This thesis demonstrates the advantages and disadvantages of investigated p-type SiGe MOSFETs with high Ge content Si1#xGex p-channel grown on Si1#yGey virtual substrate (VS) (x "0'7$0'9, y "0'3$0'5) in comparison with conventional Si devices. The ways to overcome current difficulties in conventional Si technology and mixed SiGe-Si technology are shown. Current-voltage (I-V) and capacitance-voltage (C-V) DC characteristics for p-channel Si/Si1#xGex/Si1#yGey hetero-MOSFETs with high Ge content (x "0'7$0'9, y"0'3$0'5) are reported. Enhancement in the maximum drain current for the p-SiGe devices in comparison with p-Si control is 2.5-3.0 times. DC characteristic simulations of SiGe p-channel MOSFETs were used to improve the accuracy of MOSFET and heterostructure parameters extraction. Calibrated during the simulation theoretical models were used for future design. The effective mobility, the source-drain access resistance, the doping profile, the layers thickness, oxide/semiconductor interface charge and other important characteristics were extracted. The effective mobility values, extracted for p-Si0%3Ge0%7 MOSFETs, exceed the hole mobility in a conventional Si p-MOS device by a factor of 3.5 and reach the mobility of conventional Si n-MOS transistors. The peak value of me f f = 760 cm2V#1s#1 at field 0.08 MVcm#1 was obtained for p-Si/Si0%2Ge0%8/ Si0%5Ge0%5 MOSFETs. Efficiency of special n-type doped layer, also known as "punch-through" stopper, introduced into heterostructure is shown. Perfect I-V and also low frequency noise characteristics of investigated MOSFET show that the p-type Si/Si1#xGex/Si1#yGey (x "0'7 $0'9, x$y "0'3$0'4) heterostructures with "punch-through" stopper could be very impressive opportunity to conventional Si for modern semiconductor industry. For the first time, quantitative explanation of the low frequency noise reduction in metamorphic, high Ge content, SiGe p-MOSFETs compared to Si p-MOSFETs have been proposed. Quantitative analysis demonstrates the importance of both carrier number fluctuations and correlated mobility fluctuations (CMF) components to the 1/ f noise of surface channel Si p-MOSFET, but the absence of CMF for buried channel p-Si0%3Ge0%7 and p- Si0%2Ge0%8 MOSFETs. The low frequency noise was measured to be three times smaller for a 0.55 mm effective gate length p-Si0%3Ge0%7 MOSFET than the Si control, at linear regime (VDS = -50 mV) and high gate overdrive voltage (Vgt= -1.5 V). This result is very important, because we have reduction in LF noise at high gate overdrive voltages, which are typical for analogue and power electronics application. Both DC and low frequency noise characteristics show that access source and drain resistance for metamorphic p-SiGe MOSFETs (RS +RD ,1.5-2.0kW !mm) roughly 2 times lower then for conventional p-Si MOSFETs