Functional nanoelectronic devices: single-electron transport, memristivity, and thermoelectricity in nanoscale flms using self-assembly and graphene

This dissertation reports on several experimental projects studying electronic transport in thin-flm electronic devices. Self-assembly methods and graphene were used to realise devices contacting films of self-assembled PbS quantum dots. The devices have exhibited single-electron tunnelling with a high yield. The electrical properties of the junctions are studied individually and collectively using statistical tools to extract correlations between device geometries and electrical data. The dissertation includes discussion of the theory of relevant electronic transport including numerical simulations. Several initiated projects deriving from this work are introduced. A second device reported in this thesis is a memristive switch. Contacting thin films of Al2O3 with graphene delivered junctions which exhibit memristive behaviour with an ultrahigh on-off conductance ratio. The conduction state of the junctions is correlated with morphological changes in the devices, whereby conductive flament formation in the junction is found to lead to electrically-controllable and reversible gas encapsulation in bubbles in the structure. The device is measured electrically and topographically, and the correlation between the two aspects is studied. A discussion of memristive conduction is included with numerical simulations. A third section reports on a project studying thermoelectricity in self-assembled molecular junctions, as they show potential for improved thermoelectric efficiency for energy harvesting; this is discussed in the dissertation. Strategies to benchmark the studies are presented with relevant devices fabricated and measured. These include the development of a measurement protocol to study thermoelectricity in devices, studies of electrical coupling between various molecular structures and graphene electrodes, molecular-structure dependence of electrical and thermal conductance of junctions. Preliminary results and on-going work are discussed.I want to thank the Semiconductor Physics Group of the Cavendish Laboratory, the Semiconductor Physics Group of the Institute of Physics, the Cambridge NanoDTC, and Fitzwilliam College, Cambridge for their support. I want also to thank the collaborators acknowledged in the thesis for contributions in materials and services

A Survey on Reservoir Computing and its Interdisciplinary Applications Beyond Traditional Machine Learning

Reservoir computing (RC), first applied to temporal signal processing, is a recurrent neural network in which neurons are randomly connected. Once initialized, the connection strengths remain unchanged. Such a simple structure turns RC into a non-linear dynamical system that maps low-dimensional inputs into a high-dimensional space. The model's rich dynamics, linear separability, and memory capacity then enable a simple linear readout to generate adequate responses for various applications. RC spans areas far beyond machine learning, since it has been shown that the complex dynamics can be realized in various physical hardware implementations and biological devices. This yields greater flexibility and shorter computation time. Moreover, the neuronal responses triggered by the model's dynamics shed light on understanding brain mechanisms that also exploit similar dynamical processes. While the literature on RC is vast and fragmented, here we conduct a unified review of RC's recent developments from machine learning to physics, biology, and neuroscience. We first review the early RC models, and then survey the state-of-the-art models and their applications. We further introduce studies on modeling the brain's mechanisms by RC. Finally, we offer new perspectives on RC development, including reservoir design, coding frameworks unification, physical RC implementations, and interaction between RC, cognitive neuroscience and evolution.Comment: 51 pages, 19 figures, IEEE Acces

Energetically deposited tin oxide: characterization and device applications

Semiconductor oxides are promising materials that have made impressive progress in recent years, challenging the dominance of silicon not only in conventional devices including field-effect transistors but being amenable to next-generation electronic devices such as memristors. Although a variety of oxides have been explored, tin oxide has been an interesting material for researchers when offering p-type characteristics of tin monoxide SnO and n-type characteristics in tin dioxide SnO2. While SnO2 is easy to grow and well suited for a wide range of applications, it is difficult to form p-type SnO due to its metastability where it forms into the more stable phase SnO2. The work presented in this Doctoral Dissertation focus on exploring the characteristics and applications of energetically deposited tin oxide thin films. The tin oxide film deposited using high-power impulse magnetron sputtering was found to be mixed-phase nanocrystalline SnO and SnO2 in which SnO2 is dominant. The high resistivity, low carrier concentration and low mobility in the as-deposited and annealed samples hindered the application of the high-power impulse magnetron sputtering (HiPIMS) SnOx in thin film transistors, however, suggested suitability for these films as a memristive material. A small but quantifiable variation in film stoichiometry (Sn:O) resulting from the off-axis deposition led to the formation of two different types of memristive devices, namely filamentary and nanoparticle network memristors. Both devices exhibited stable volatile bidirectional resistive switching with a ratio between high resistance and low resistance of more than two orders of magnitude. However, their underlying resistive switching mechanisms and device characteristics were significantly different. Synaptic-like behaviours were observed on both filamentary devices (FDs) and nanoparticle network devices (NNDs), highlighting their potential for information processing in neuromorphic computing systems. While a FD can become only an individual cell in reservoir computing circuits, an NND can be implemented as a reservoir due to their available inter-connectivity which is required for reservoir computing

Single Electron Devices and Circuit Architectures: Modeling Techniques, Dynamic Characteristics, and Reliability Analysis

The Single Electron (SE) technology is an important approach to enabling further feature size reduction and circuit performance improvement. However, new methods are required for device modeling, circuit behavior description, and reliability analysis with this technology due to its unique operation mechanism. In this thesis, a new macro-model of SE turnstile is developed to describe its physical characteristics for large-scale circuit simulation and design. Based on this model, several novel circuit architectures are proposed and implemented to further demonstrate the advantages of SE technique. The dynamic behavior of SE circuits, which is different from their CMOS counterpart, is also investigated using a statistical method. With the unreliable feature of SE devices in mind, a fast and recursive algorithm is developed to evaluate the reliability of SE logic circuits in a more efficient and effective manner

On-Chip Learning and Inference Acceleration of Sparse Representations

abstract: The past decade has seen a tremendous surge in running machine learning (ML) functions on mobile devices, from mere novelty applications to now indispensable features for the next generation of devices. While the mobile platform capabilities range widely, long battery life and reliability are common design concerns that are crucial to remain competitive. Consequently, state-of-the-art mobile platforms have become highly heterogeneous by combining a powerful CPUs with GPUs to accelerate the computation of deep neural networks (DNNs), which are the most common structures to perform ML operations. But traditional von Neumann architectures are not optimized for the high memory bandwidth and massively parallel computation demands required by DNNs. Hence, propelling research into non-von Neumann architectures to support the demands of DNNs. The re-imagining of computer architectures to perform efficient DNN computations requires focusing on the prohibitive demands presented by DNNs and alleviating them. The two central challenges for efficient computation are (1) large memory storage and movement due to weights of the DNN and (2) massively parallel multiplications to compute the DNN output. Introducing sparsity into the DNNs, where certain percentage of either the weights or the outputs of the DNN are zero, greatly helps with both challenges. This along with algorithm-hardware co-design to compress the DNNs is demonstrated to provide efficient solutions to greatly reduce the power consumption of hardware that compute DNNs. Additionally, exploring emerging technologies such as non-volatile memories and 3-D stacking of silicon in conjunction with algorithm-hardware co-design architectures will pave the way for the next generation of mobile devices. Towards the objectives stated above, our specific contributions include (a) an architecture based on resistive crosspoint array that can update all values stored and compute matrix vector multiplication in parallel within a single cycle, (b) a framework of training DNNs with a block-wise sparsity to drastically reduce memory storage and total number of computations required to compute the output of DNNs, (c) the exploration of hardware implementations of sparse DNNs and architectural guidelines to reduce power consumption for the implementations in monolithic 3D integrated circuits, and (d) a prototype chip in 65nm CMOS accelerator for long-short term memory networks trained with the proposed block-wise sparsity scheme.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Electronic and Optoelectronic Properties of Two-Dimensional Heterostructures for Next-Generation Device Technologies

Since monolayer graphene was isolated in 2004, there has been significant interest in integrating layered materials into innovative device designs and hybrid materials to help solve pressing technological challenges. This is partially because they can typically be thinned to a two-dimensional (2D) form without suffering from roughness-induced scattering and can exhibit thickness-dependent variations in properties such as their energy band gap. This dissertation reports on investigations of electronic and optoelectronic device physics in 2D material heterostructures. The investigation of electronic device physics focuses on the interface between 2D molybdenum disulfide (MoS2) and gold (Au), which behaves as a resistive switching element (RSE). RSEs are microelectronic switches whose resistances depend on the history of electrical stimuli they have experienced. Prototype computer memory cells utilizing RSEs have demonstrated non-volatile switching behavior and high data retention times, likely enabling more environmentally-conscious computing. The ultimate degree of lateral scaling that MoS2-based RSEs can attain is currently unknown, but of great importance for determining their role in beyond-silicon computing applications. This work demonstrates, using the metallic tip of a scanning tunneling microscope as an electrode in a model MoS2-based RSE, that switching events can be recorded even in device areas on the order of tens of nanometers across without the use of lithographic techniques. The investigation of optoelectronic device physics focuses on utilizing hexagonal boron nitride (hBN), an electrical insulator with an ~ 6.0 eV band gap, to fabricate ultraviolet photodetectors. The main advantage that hBN-based detectors have over Si-based detectors is that they are inherently insensitive to visible and infrared light without needing bulky or expensive optical band pass filters, thus eliminating signal contamination from ambient sources. This work describes the fabrication and characterization of several detectors featuring vertical designs, allowing for greater degrees of both vertical and lateral scaling