Providing Bi-Directional, Analog, and Differential Signal Transmission Capability to an Electronic Prototyping Platform

RÉSUMÉ Les réseaux d’interconnexions programmables (FPIN) se retrouvent largement utilisés dans plusieurs structures bien connues telles que les FPGA, les plateformes de prototypages ainsi que dans plusieurs architectures de réseaux intégrés. Le but de la présente thèse est d’améliorer la structure actuelle des FPIN ainsi que les plateformes de prototypages se basant sur cette technologie afin d’y intégrer d’autres fonctionnalités telles que des interfaces pour les signaux bidirectionnels de type drain-ouvert, les signaux analogiques ou bien les signaux différentiels. Cette thèse présente trois différents circuits qui ont été implémentés dans cette optique. Les interconnexions de ces trois circuits peuvent être reconfigurées pour supporter une interface de type bidirectionnelle drain-ouvert, de type analogique ou différentielle, le tout au travers un réseau d’interconnexions configurable numérique unidirectionnel, ou FPIN. Le besoin d’une telle interface fut tout d’abord envisagé dans le contexte du WaferBoard, qui consiste en une plateforme reconfigurable de prototypage pour les systèmes électroniques. Le cœur de ce WaferBoard consiste en un circuit intégré à l’échelle d’une tranche entière de silicium, qui est constitué d’une matrice bidimensionnelle de cellules. Une large partie de la surface disponible s’en retrouve déjà utilisée par des plots configurables (CIO), l’aiguillage des multiplexeurs du FPIN, des registres dédiés à la chaine JTAG et d’autres circuiteries de contrôle. De ce fait, il en devient primordial que les interfaces bidirectionnelle drain-ouvert, analogique et différentielle soit les plus compactes possibles. Puisque ces circuits d’interfaces seront dédiés pour une plateforme utilisant une tranche de silicium (wafer-scale), l’architecture de ces derniers doit être robuste en regard des variations de procédé, de la température ainsi que de l’alimentation. La première contribution de cette thèse est l’élaboration et la conception d’une interface de type drain-ouvert ainsi que de son support d’interconnexion bidirectionnel utilisant un réseau numérique unidirectionnel à signalisation asymétrique (à l’opposé de la signalisation différentielle) FPIN. L’interface proposée peut interconnecter plusieurs nœuds d’un FPIN. À l’aide de cette interface, le réseau d’interconnexions peut imiter le comportement et le fonctionnement d’un bus de type drain-ouvert (ou collecteur-ouvert) (tel qu’utilisé par le protocole I2C). De ce fait, plusieurs plots de type drain-ouvert provenant d’une multitude de circuits-intégrés (ICs) différents peuvent y être connectés au travers le FPIN à l’aide de l’interface proposée.----------ABSTRACT Field programmable interconnection networks (FPINs) are ubiquitously found embedded in field-programmable gate arrays (FPGAs), in prototyping platforms, and in many Network-on-Chip architectures. The aim of this research was to augment the application domains of current FPIN-based prototyping and emulation platforms by supporting open-drain bi-directional signals, analog signals or differential signals. Three interface circuits have been elaborated and developed to that end in this thesis. These three interface circuits can support reconfigurable routing of open-drain bi-directional, analog and differential signals through an uni-directional digital FPIN. The need for such interface circuits were originally conceived in the context of the WaferBoard, a system prototyping platform. The core of the WaferBoard is a wafer-scale IC that is composed of a two dimensional array of unit cells. Available area was already over-utilized by the configurable I/O (CIO) buffers, crossbar multiplexers of the FPIN, registers of the JTAG chain, and other control circuits. Thus, the interface circuits for open-drain bi-directional, analog and differential signaling had to be made very compact. As the implementation of these interface circuits target “wafer-scale” integration, these interface circuits had to be very robust to parametric variations (process, temperature, power supply). The first contribution of this thesis is the elaboration and development of an open-drain interface circuit and a corresponding interconnect topology to support bi-directional communication through the uni-directional digital FPIN of prototyping platforms. The proposed interface can interconnect multiple nodes in a FPIN. With that interface, the interconnection network imitates the behavior of open-drain (or open-collector) buses (e.g., those following the I2C protocol). Thus, multiple open-drain I/Os from external integrated circuits (ICs) can be connected together through the FPIN by the proposed interface circuit. The interface that has been fabricated in a 0.13 µm CMOS technology takes 65 µm × 22 µm per pin. Test results show that several instances of this interface can be interconnected through the proposed interconnect topology

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

© 2016 Cheung, Schultz and Luk.NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation

Memory and information processing in neuromorphic systems

A striking difference between brain-inspired neuromorphic processors and current von Neumann processors architectures is the way in which memory and processing is organized. As Information and Communication Technologies continue to address the need for increased computational power through the increase of cores within a digital processor, neuromorphic engineers and scientists can complement this need by building processor architectures where memory is distributed with the processing. In this paper we present a survey of brain-inspired processor architectures that support models of cortical networks and deep neural networks. These architectures range from serial clocked implementations of multi-neuron systems to massively parallel asynchronous ones and from purely digital systems to mixed analog/digital systems which implement more biological-like models of neurons and synapses together with a suite of adaptation and learning mechanisms analogous to the ones found in biological nervous systems. We describe the advantages of the different approaches being pursued and present the challenges that need to be addressed for building artificial neural processing systems that can display the richness of behaviors seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed neuromorphic computing platforms and system

Low-power CMOS digital-pixel Imagers for high-speed uncooled PbSe IR applications

This PhD dissertation describes the research and development of a new low-cost medium wavelength infrared MWIR monolithic imager technology for high-speed uncooled industrial applications. It takes the baton on the latest technological advances in the field of vapour phase deposition (VPD) PbSe-based medium wavelength IR (MWIR) detection accomplished by the industrial partner NIT S.L., adding fundamental knowledge on the investigation of novel VLSI analog and mixed-signal design techniques at circuit and system levels for the development of the readout integrated device attached to the detector. The work supports on the hypothesis that, by the use of the preceding design techniques, current standard inexpensive CMOS technologies fulfill all operational requirements of the VPD PbSe detector in terms of connectivity, reliability, functionality and scalability to integrate the device. The resulting monolithic PbSe-CMOS camera must consume very low power, operate at kHz frequencies, exhibit good uniformity and fit the CMOS read-out active pixels in the compact pitch of the focal plane, all while addressing the particular characteristics of the MWIR detector: high dark-to-signal ratios, large input parasitic capacitance values and remarkable mismatching in PbSe integration. In order to achieve these demands, this thesis proposes null inter-pixel crosstalk vision sensor architectures based on a digital-only focal plane array (FPA) of configurable pixel sensors. Each digital pixel sensor (DPS) cell is equipped with fast communication modules, self-biasing, offset cancellation, analog-to-digital converter (ADC) and fixed pattern noise (FPN) correction. In-pixel power consumption is minimized by the use of comprehensive MOSFET subthreshold operation. The main aim is to potentiate the integration of PbSe-based infra-red (IR)-image sensing technologies so as to widen its use, not only in distinct scenarios, but also at different stages of PbSe-CMOS integration maturity. For this purpose, we posit to investigate a comprehensive set of functional blocks distributed in two parallel approaches: • Frame-based “Smart” MWIR imaging based on new DPS circuit topologies with gain and offset FPN correction capabilities. This research line exploits the detector pitch to offer fully-digital programmability at pixel level and complete functionality with input parasitic capacitance compensation and internal frame memory. • Frame-free “Compact”-pitch MWIR vision based on a novel DPS lossless analog integrator and configurable temporal difference, combined with asynchronous communication protocols inside the focal plane. This strategy is conceived to allow extensive pitch compaction and readout speed increase by the suppression of in-pixel digital filtering, and the use of dynamic bandwidth allocation in each pixel of the FPA. In order make the electrical validation of first prototypes independent of the expensive PbSe deposition processes at wafer level, investigation is extended as well to the development of affordable sensor emulation strategies and integrated test platforms specifically oriented to image read-out integrated circuits. DPS cells, imagers and test chips have been fabricated and characterized in standard 0.15μm 1P6M, 0.35μm 2P4M and 2.5μm 2P1M CMOS technologies, all as part of research projects with industrial partnership. The research has led to the first high-speed uncooled frame-based IR quantum imager monolithically fabricated in a standard VLSI CMOS technology, and has given rise to the Tachyon series [1], a new line of commercial IR cameras used in real-time industrial, environmental and transportation control systems. The frame-free architectures investigated in this work represent a firm step forward to push further pixel pitch and system bandwidth up to the limits imposed by the evolving PbSe detector in future generations of the device.La present tesi doctoral descriu la recerca i el desenvolupament d'una nova tecnologia monolítica d'imatgeria infraroja de longitud d'ona mitja (MWIR), no refrigerada i de baix cost, per a usos industrials d'alta velocitat. El treball pren el relleu dels últims avenços assolits pel soci industrial NIT S.L. en el camp dels detectors MWIR de PbSe depositats en fase vapor (VPD), afegint-hi coneixement fonamental en la investigació de noves tècniques de disseny de circuits VLSI analògics i mixtes pel desenvolupament del dispositiu integrat de lectura unit al detector pixelat. Es parteix de la hipòtesi que, mitjançant l'ús de les esmentades tècniques de disseny, les tecnologies CMOS estàndard satisfan tots els requeriments operacionals del detector VPD PbSe respecte a connectivitat, fiabilitat, funcionalitat i escalabilitat per integrar de forma econòmica el dispositiu. La càmera PbSe-CMOS resultant ha de consumir molt baixa potència, operar a freqüències de kHz, exhibir bona uniformitat, i encabir els píxels actius CMOS de lectura en el pitch compacte del pla focal de la imatge, tot atenent a les particulars característiques del detector: altes relacions de corrent d'obscuritat a senyal, elevats valors de capacitat paràsita a l'entrada i dispersions importants en el procés de fabricació. Amb la finalitat de complir amb els requisits previs, es proposen arquitectures de sensors de visió de molt baix acoblament interpíxel basades en l'ús d'una matriu de pla focal (FPA) de píxels actius exclusivament digitals. Cada píxel sensor digital (DPS) està equipat amb mòduls de comunicació d'alta velocitat, autopolarització, cancel·lació de l'offset, conversió analògica-digital (ADC) i correcció del soroll de patró fixe (FPN). El consum en cada cel·la es minimitza fent un ús exhaustiu del MOSFET operant en subllindar. L'objectiu últim és potenciar la integració de les tecnologies de sensat d'imatge infraroja (IR) basades en PbSe per expandir-ne el seu ús, no només a diferents escenaris, sinó també en diferents estadis de maduresa de la integració PbSe-CMOS. En aquest sentit, es proposa investigar un conjunt complet de blocs funcionals distribuïts en dos enfocs paral·lels: - Dispositius d'imatgeria MWIR "Smart" basats en frames utilitzant noves topologies de circuit DPS amb correcció de l'FPN en guany i offset. Aquesta línia de recerca exprimeix el pitch del detector per oferir una programabilitat completament digital a nivell de píxel i plena funcionalitat amb compensació de la capacitat paràsita d'entrada i memòria interna de fotograma. - Dispositius de visió MWIR "Compact"-pitch "frame-free" en base a un novedós esquema d'integració analògica en el DPS i diferenciació temporal configurable, combinats amb protocols de comunicació asíncrons dins del pla focal. Aquesta estratègia es concep per permetre una alta compactació del pitch i un increment de la velocitat de lectura, mitjançant la supressió del filtrat digital intern i l'assignació dinàmica de l'ample de banda a cada píxel de l'FPA. Per tal d'independitzar la validació elèctrica dels primers prototips respecte a costosos processos de deposició del PbSe sensor a nivell d'oblia, la recerca s'amplia també al desenvolupament de noves estratègies d'emulació del detector d'IR i plataformes de test integrades especialment orientades a circuits integrats de lectura d'imatge. Cel·les DPS, dispositius d'imatge i xips de test s'han fabricat i caracteritzat, respectivament, en tecnologies CMOS estàndard 0.15 micres 1P6M, 0.35 micres 2P4M i 2.5 micres 2P1M, tots dins el marc de projectes de recerca amb socis industrials. Aquest treball ha conduït a la fabricació del primer dispositiu quàntic d'imatgeria IR d'alta velocitat, no refrigerat, basat en frames, i monolíticament fabricat en tecnologia VLSI CMOS estàndard, i ha donat lloc a Tachyon, una nova línia de càmeres IR comercials emprades en sistemes de control industrial, mediambiental i de transport en temps real.Postprint (published version

Membrane Deflection-based Fabrication and Design Automation for Integrated Acoustofluidics

Continuous-flow microfluidic large-scale integration (mLSI) is a developing field first introduced in the early 2000s, that continues to offer promising solutions to many biochemical, biophysical and biomedical problems. In his seminal paper, Thorsen et al. 2002 demonstrated the fabrication of high-density microfluidic systems capable of complex fluidic routing in combinatory arrays of multiplexors, mixers, and storage assemblies integrated with micromechanical valves. mLSI has been a powerful tool for scientific research by allowing for dramatic reduction in the volume of reagent needed for experimentation and offering highly parallelizable and dynamic process flows. These systems have since been the focus of strong interdisciplinary academic research efforts. Despite the success in scientific applications, the mLSI technologies have not found widespread use in commercial environments. One critical issue preventing mLSI to realize its full potential is the need for specialized fabrication techniques that are scalable and more suitable for the unique requirements of biology. The work presented here demonstrates an mLSI integrated acoustofluidic platform that offers versatility while maintaining a robust fabrication process. In particular, conductive liquid metal-based acoustic transducers integrated with micromechanical valves to facilitate dynamic switching of the resonant frequency of the device and generated surface acoustic waves (SAWs) is demonstrated. Shortcomings in the fabrication of fluidic channels for mLSI integrated acoustofluidic applications are examined, and solutions to these problems are presented. A novel and scalable soft-lithographic method is introduced, that allows for the fabrication of large valvable channels with tunable height that exceeds practical limitations dictated by previous photolithographic techniques. A thorough characterization of this method and demonstration of its robustness are included here as a promising data to promote further exploration of the technique as a viable commercial solution for the fabrication of many classes of mLSI bio-devices. The testing of a computeraided design software, Columba, is briefly discussed

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Cross-Layer Rapid Prototyping and Synthesis of Application-Specific and Reconfigurable Many-accelerator Platforms

Technological advances of recent years laid the foundation consolidation of informatisationof society, impacting on economic, political, cultural and socialdimensions. At the peak of this realization, today, more and more everydaydevices are connected to the web, giving the term ”Internet of Things”. The futureholds the full connection and interaction of IT and communications systemsto the natural world, delimiting the transition to natural cyber systems and offeringmeta-services in the physical world, such as personalized medical care, autonomoustransportation, smart energy cities etc. . Outlining the necessities of this dynamicallyevolving market, computer engineers are required to implement computingplatforms that incorporate both increased systemic complexity and also cover awide range of meta-characteristics, such as the cost and design time, reliabilityand reuse, which are prescribed by a conflicting set of functional, technical andconstruction constraints. This thesis aims to address these design challenges bydeveloping methodologies and hardware/software co-design tools that enable therapid implementation and efficient synthesis of architectural solutions, which specifyoperating meta-features required by the modern market. Specifically, this thesispresents a) methodologies to accelerate the design flow for both reconfigurableand application-specific architectures, b) coarse-grain heterogeneous architecturaltemplates for processing and communication acceleration and c) efficient multiobjectivesynthesis techniques both at high abstraction level of programming andphysical silicon level.Regarding to the acceleration of the design flow, the proposed methodologyemploys virtual platforms in order to hide architectural details and drastically reducesimulation time. An extension of this framework introduces the systemicco-simulation using reconfigurable acceleration platforms as co-emulation intermediateplatforms. Thus, the development cycle of a hardware/software productis accelerated by moving from a vertical serial flow to a circular interactive loop.Moreover the simulation capabilities are enriched with efficient detection and correctiontechniques of design errors, as well as control methods of performancemetrics of the system according to the desired specifications, during all phasesof the system development. In orthogonal correlation with the aforementionedmethodological framework, a new architectural template is proposed, aiming atbridging the gap between design complexity and technological productivity usingspecialized hardware accelerators in heterogeneous systems-on-chip and networkon-chip platforms. It is presented a novel co-design methodology for the hardwareaccelerators and their respective programming software, including the tasks allocationto the available resources of the system/network. The introduced frameworkprovides implementation techniques for the accelerators, using either conventionalprogramming flows with hardware description language or abstract programmingmodel flows, using techniques from high-level synthesis. In any case, it is providedthe option of systemic measures optimization, such as the processing speed,the throughput, the reliability, the power consumption and the design silicon area.Finally, on addressing the increased complexity in design tools of reconfigurablesystems, there are proposed novel multi-objective optimization evolutionary algo-rithms which exploit the modern multicore processors and the coarse-grain natureof multithreaded programming environments (e.g. OpenMP) in order to reduce theplacement time, while by simultaneously grouping the applications based on theirintrinsic characteristics, the effectively explore the design space effectively.The efficiency of the proposed architectural templates, design tools and methodologyflows is evaluated in relation to the existing edge solutions with applicationsfrom typical computing domains, such as digital signal processing, multimedia andarithmetic complexity, as well as from systemic heterogeneous environments, suchas a computer vision system for autonomous robotic space navigation and manyacceleratorsystems for HPC and workstations/datacenters. The results strengthenthe belief of the author, that this thesis provides competitive expertise to addresscomplex modern - and projected future - design challenges.Οι τεχνολογικές εξελίξεις των τελευταίων ετών έθεσαν τα θεμέλια εδραίωσης της πληροφοριοποίησης της κοινωνίας, επιδρώντας σε οικονομικές,πολιτικές, πολιτιστικές και κοινωνικές διαστάσεις. Στο απόγειο αυτής τη ςπραγμάτωσης, σήμερα, ολοένα και περισσότερες καθημερινές συσκευές συνδέονται στο παγκόσμιο ιστό, αποδίδοντας τον όρο «Ίντερνετ των πραγμάτων».Το μέλλον επιφυλάσσει την πλήρη σύνδεση και αλληλεπίδραση των συστημάτων πληροφορικής και επικοινωνιών με τον φυσικό κόσμο, οριοθετώντας τη μετάβαση στα συστήματα φυσικού κυβερνοχώρου και προσφέροντας μεταυπηρεσίες στον φυσικό κόσμο όπως προσωποποιημένη ιατρική περίθαλψη, αυτόνομες μετακινήσεις, έξυπνες ενεργειακά πόλεις κ.α. . Σκιαγραφώντας τις ανάγκες αυτής της δυναμικά εξελισσόμενης αγοράς, οι μηχανικοί υπολογιστών καλούνται να υλοποιήσουν υπολογιστικές πλατφόρμες που αφενός ενσωματώνουν αυξημένη συστημική πολυπλοκότητα και αφετέρου καλύπτουν ένα ευρύ φάσμα μεταχαρακτηριστικών, όπως λ.χ. το κόστος σχεδιασμού, ο χρόνος σχεδιασμού, η αξιοπιστία και η επαναχρησιμοποίηση, τα οποία προδιαγράφονται από ένα αντικρουόμενο σύνολο λειτουργικών, τεχνολογικών και κατασκευαστικών περιορισμών. Η παρούσα διατριβή στοχεύει στην αντιμετώπιση των παραπάνω σχεδιαστικών προκλήσεων, μέσω της ανάπτυξης μεθοδολογιών και εργαλείων συνσχεδίασης υλικού/λογισμικού που επιτρέπουν την ταχεία υλοποίηση καθώς και την αποδοτική σύνθεση αρχιτεκτονικών λύσεων, οι οποίες προδιαγράφουν τα μετα-χαρακτηριστικά λειτουργίας που απαιτεί η σύγχρονη αγορά. Συγκεκριμένα, στα πλαίσια αυτής της διατριβής, παρουσιάζονται α) μεθοδολογίες επιτάχυνσης της ροής σχεδιασμού τόσο για επαναδιαμορφούμενες όσο και για εξειδικευμένες αρχιτεκτονικές, β) ετερογενή αδρομερή αρχιτεκτονικά πρότυπα επιτάχυνσης επεξεργασίας και επικοινωνίας και γ) αποδοτικές τεχνικές πολυκριτηριακής σύνθεσης τόσο σε υψηλό αφαιρετικό επίπεδο προγραμματισμού,όσο και σε φυσικό επίπεδο πυριτίου.Αναφορικά προς την επιτάχυνση της ροής σχεδιασμού, προτείνεται μια μεθοδολογία που χρησιμοποιεί εικονικές πλατφόρμες, οι οποίες αφαιρώντας τις αρχιτεκτονικές λεπτομέρειες καταφέρνουν να μειώσουν σημαντικά το χρόνο εξομοίωσης. Παράλληλα, εισηγείται η συστημική συν-εξομοίωση με τη χρήση επαναδιαμορφούμενων πλατφορμών, ως μέσων επιτάχυνσης. Με αυτόν τον τρόπο, ο κύκλος ανάπτυξης ενός προϊόντος υλικού, μετατεθειμένος από την κάθετη σειριακή ροή σε έναν κυκλικό αλληλεπιδραστικό βρόγχο, καθίσταται ταχύτερος, ενώ οι δυνατότητες προσομοίωσης εμπλουτίζονται με αποδοτικότερες μεθόδους εντοπισμού και διόρθωσης σχεδιαστικών σφαλμάτων, καθώς και μεθόδους ελέγχου των μετρικών απόδοσης του συστήματος σε σχέση με τις επιθυμητές προδιαγραφές, σε όλες τις φάσεις ανάπτυξης του συστήματος. Σε ορθογώνια συνάφεια με το προαναφερθέν μεθοδολογικό πλαίσιο, προτείνονται νέα αρχιτεκτονικά πρότυπα που στοχεύουν στη γεφύρωση του χάσματος μεταξύ της σχεδιαστικής πολυπλοκότητας και της τεχνολογικής παραγωγικότητας, με τη χρήση συστημάτων εξειδικευμένων επιταχυντών υλικού σε ετερογενή συστήματα-σε-ψηφίδα καθώς και δίκτυα-σε-ψηφίδα. Παρουσιάζεται κατάλληλη μεθοδολογία συν-σχεδίασης των επιταχυντών υλικού και του λογισμικού προκειμένου να αποφασισθεί η κατανομή των εργασιών στους διαθέσιμους πόρους του συστήματος/δικτύου. Το μεθοδολογικό πλαίσιο προβλέπει την υλοποίηση των επιταχυντών είτε με συμβατικές μεθόδους προγραμματισμού σε γλώσσα περιγραφής υλικού είτε με αφαιρετικό προγραμματιστικό μοντέλο με τη χρήση τεχνικών υψηλού επιπέδου σύνθεσης. Σε κάθε περίπτωση, δίδεται η δυνατότητα στο σχεδιαστή για βελτιστοποίηση συστημικών μετρικών, όπως η ταχύτητα επεξεργασίας, η ρυθμαπόδοση, η αξιοπιστία, η κατανάλωση ενέργειας και η επιφάνεια πυριτίου του σχεδιασμού. Τέλος, προκειμένου να αντιμετωπισθεί η αυξημένη πολυπλοκότητα στα σχεδιαστικά εργαλεία επαναδιαμορφούμενων συστημάτων, προτείνονται νέοι εξελικτικοί αλγόριθμοι πολυκριτηριακής βελτιστοποίησης, οι οποίοι εκμεταλλευόμενοι τους σύγχρονους πολυπύρηνους επεξεργαστές και την αδρομερή φύση των πολυνηματικών περιβαλλόντων προγραμματισμού (π.χ. OpenMP), μειώνουν το χρόνο επίλυσης του προβλήματος της τοποθέτησης των λογικών πόρων σε φυσικούς,ενώ ταυτόχρονα, ομαδοποιώντας τις εφαρμογές βάση των εγγενών χαρακτηριστικών τους, διερευνούν αποτελεσματικότερα το χώρο σχεδίασης.Η αποδοτικότητά των προτεινόμενων αρχιτεκτονικών προτύπων και μεθοδολογιών επαληθεύτηκε σε σχέση με τις υφιστάμενες λύσεις αιχμής τόσο σε αυτοτελής εφαρμογές, όπως η ψηφιακή επεξεργασία σήματος, τα πολυμέσα και τα προβλήματα αριθμητικής πολυπλοκότητας, καθώς και σε συστημικά ετερογενή περιβάλλοντα, όπως ένα σύστημα όρασης υπολογιστών για αυτόνομα διαστημικά ρομποτικά οχήματα και ένα σύστημα πολλαπλών επιταχυντών υλικού για σταθμούς εργασίας και κέντρα δεδομένων, στοχεύοντας εφαρμογές υψηλής υπολογιστικής απόδοσης (HPC). Τα αποτελέσματα ενισχύουν την πεποίθηση του γράφοντα, ότι η παρούσα διατριβή παρέχει ανταγωνιστική τεχνογνωσία για την αντιμετώπιση των πολύπλοκων σύγχρονων και προβλεπόμενα μελλοντικών σχεδιαστικών προκλήσεων

Principles, fundamentals, and applications of programmable integrated photonics

[EN] Programmable integrated photonics is an emerging new paradigm that aims at designing common integrated optical hardware resource configurations, capable of implementing an unconstrained variety of functionalities by suitable programming, following a parallel but not identical path to that of integrated electronics in the past two decades of the last century. Programmable integrated photonics is raising considerable interest, as it is driven by the surge of a considerable number of new applications in the fields of telecommunications, quantum information processing, sensing, and neurophotonics, calling for flexible, reconfigurable, low-cost, compact, and low-power-consuming devices that can cooperate with integrated electronic devices to overcome the limitation expected by the demise of Moore¿s Law. Integrated photonic devices exploiting full programmability are expected to scale from application-specific photonic chips (featuring a relatively low number of functionalities) up to very complex application-agnostic complex subsystems much in the same way as field programmable gate arrays and microprocessors operate in electronics. Two main differences need to be considered. First, as opposed to integrated electronics, programmable integrated photonics will carry analog operations over the signals to be processed. Second, the scale of integration density will be several orders of magnitude smaller due to the physical limitations imposed by the wavelength ratio of electrons and light wave photons. The success of programmable integrated photonics will depend on leveraging the properties of integrated photonic devices and, in particular, on research into suitable interconnection hardware architectures that can offer a very high spatial regularity as well as the possibility of independently setting (with a very low power consumption) the interconnection state of each connecting element. Integrated multiport interferometers and waveguide meshes provide regular and periodic geometries, formed by replicating unit elements and cells, respectively. In the case of waveguide meshes, the cells can take the form of a square, hexagon, or triangle, among other configurations. Each side of the cell is formed by two integrated waveguides connected by means of a Mach¿Zehnder interferometer or a tunable directional coupler that can be operated by means of an output control signal as a crossbar switch or as a variable coupler with independent power division ratio and phase shift. In this paper, we provide the basic foundations and principles behind the construction of these complex programmable circuits. We also review some practical aspects that limit the programming and scalability of programmable integrated photonics and provide an overview of some of the most salient applications demonstrated so far.European Research Council; Conselleria d'Educació, Investigació, Cultura i Esport; Ministerio de Ciencia, Innovación y Universidades; European Cooperation in Science and Technology; Horizon 2020 Framework Programme.Pérez-López, D.; Gasulla Mestre, I.; Dasmahapatra, P.; Capmany Francoy, J. (2020). Principles, fundamentals, and applications of programmable integrated photonics. Advances in Optics and Photonics. 12(3):709-786. https://doi.org/10.1364/AOP.387155709786123Lyke, J. C., Christodoulou, C. G., Vera, G. A., & Edwards, A. H. (2015). An Introduction to Reconfigurable Systems. Proceedings of the IEEE, 103(3), 291-317. doi:10.1109/jproc.2015.2397832Kaeslin, H. (2008). Digital Integrated Circuit Design. doi:10.1017/cbo9780511805172Trimberger, S. M. (2015). Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology. Proceedings of the IEEE, 103(3), 318-331. doi:10.1109/jproc.2015.2392104Mitola, J. (1995). The software radio architecture. IEEE Communications Magazine, 33(5), 26-38. doi:10.1109/35.393001Nunes, B. A. A., Mendonca, M., Nguyen, X.-N., Obraczka, K., & Turletti, T. (2014). A Survey of Software-Defined Networking: Past, Present, and Future of Programmable Networks. IEEE Communications Surveys & Tutorials, 16(3), 1617-1634. doi:10.1109/surv.2014.012214.00180Papagianni, C., Leivadeas, A., Papavassiliou, S., Maglaris, V., Cervello-Pastor, C., & Monje, A. (2013). On the optimal allocation of virtual resources in cloud computing networks. IEEE Transactions on Computers, 62(6), 1060-1071. doi:10.1109/tc.2013.31Peruzzo, A., Laing, A., Politi, A., Rudolph, T., & O’Brien, J. L. (2011). Multimode quantum interference of photons in multiport integrated devices. Nature Communications, 2(1). doi:10.1038/ncomms1228Metcalf, B. J., Thomas-Peter, N., Spring, J. B., Kundys, D., Broome, M. A., Humphreys, P. C., … Walmsley, I. A. (2013). Multiphoton quantum interference in a multiport integrated photonic device. Nature Communications, 4(1). doi:10.1038/ncomms2349Miller, D. A. B. (2013). Self-aligning universal beam coupler. Optics Express, 21(5), 6360. doi:10.1364/oe.21.006360Miller, D. A. B. (2013). Self-configuring universal linear optical component [Invited]. Photonics Research, 1(1), 1. doi:10.1364/prj.1.000001Carolan, J., Harrold, C., Sparrow, C., Martín-López, E., Russell, N. J., Silverstone, J. W., … Laing, A. (2015). Universal linear optics. Science, 349(6249), 711-716. doi:10.1126/science.aab3642Harris, N. C., Steinbrecher, G. R., Prabhu, M., Lahini, Y., Mower, J., Bunandar, D., … Englund, D. (2017). Quantum transport simulations in a programmable nanophotonic processor. Nature Photonics, 11(7), 447-452. doi:10.1038/nphoton.2017.95Birth of the programmable optical chip. (2015). Nature Photonics, 10(1), 1-1. doi:10.1038/nphoton.2015.265Zhuang, L., Roeloffzen, C. G. H., Hoekman, M., Boller, K.-J., & Lowery, A. J. (2015). Programmable photonic signal processor chip for radiofrequency applications. Optica, 2(10), 854. doi:10.1364/optica.2.000854Pérez, D., Gasulla, I., Capmany, J., & Soref, R. A. (2016). Reconfigurable lattice mesh designs for programmable photonic processors. Optics Express, 24(11), 12093. doi:10.1364/oe.24.012093Capmany, J., Gasulla, I., & Pérez, D. (2015). The programmable processor. Nature Photonics, 10(1), 6-8. doi:10.1038/nphoton.2015.254Pérez, D., Gasulla, I., Crudgington, L., Thomson, D. J., Khokhar, A. Z., Li, K., … Capmany, J. (2017). Multipurpose silicon photonics signal processor core. Nature Communications, 8(1). doi:10.1038/s41467-017-00714-1Clements, W. R., Humphreys, P. C., Metcalf, B. J., Kolthammer, W. S., & Walsmley, I. A. (2016). Optimal design for universal multiport interferometers. Optica, 3(12), 1460. doi:10.1364/optica.3.001460Perez, D., Gasulla, I., Fraile, F. J., Crudgington, L., Thomson, D. J., Khokhar, A. Z., … Capmany, J. (2017). Silicon Photonics Rectangular Universal Interferometer. Laser & Photonics Reviews, 11(6), 1700219. doi:10.1002/lpor.201700219Shen, Y., Harris, N. C., Skirlo, S., Prabhu, M., Baehr-Jones, T., Hochberg, M., … Soljačić, M. (2017). Deep learning with coherent nanophotonic circuits. Nature Photonics, 11(7), 441-446. doi:10.1038/nphoton.2017.93Ribeiro, A., Ruocco, A., Vanacker, L., & Bogaerts, W. (2016). Demonstration of a 4 × 4-port universal linear circuit. Optica, 3(12), 1348. doi:10.1364/optica.3.001348Annoni, A., Guglielmi, E., Carminati, M., Ferrari, G., Sampietro, M., Miller, D. A., … Morichetti, F. (2017). Unscrambling light—automatically undoing strong mixing between modes. Light: Science & Applications, 6(12), e17110-e17110. doi:10.1038/lsa.2017.110Perez, D., Gasulla, I., & Capmany, J. (2018). Toward Programmable Microwave Photonics Processors. Journal of Lightwave Technology, 36(2), 519-532. doi:10.1109/jlt.2017.2778741Chen, L., Hall, E., Theogarajan, L., & Bowers, J. (2011). Photonic Switching for Data Center Applications. IEEE Photonics Journal, 3(5), 834-844. doi:10.1109/jphot.2011.2166994Miller, D. A. B. (2017). Meshing optics with applications. Nature Photonics, 11(7), 403-404. doi:10.1038/nphoton.2017.104Thomas-Peter, N., Langford, N. K., Datta, A., Zhang, L., Smith, B. J., Spring, J. B., … Walmsley, I. A. (2011). Integrated photonic sensing. New Journal of Physics, 13(5), 055024. doi:10.1088/1367-2630/13/5/055024Smit, M., Leijtens, X., Ambrosius, H., Bente, E., van der Tol, J., Smalbrugge, B., … van Veldhoven, R. (2014). An introduction to InP-based generic integration technology. Semiconductor Science and Technology, 29(8), 083001. doi:10.1088/0268-1242/29/8/083001Coldren, L. A., Nicholes, S. C., Johansson, L., Ristic, S., Guzzon, R. S., Norberg, E. J., & Krishnamachari, U. (2011). High Performance InP-Based Photonic ICs—A Tutorial. Journal of Lightwave Technology, 29(4), 554-570. doi:10.1109/jlt.2010.2100807Kish, F., Nagarajan, R., Welch, D., Evans, P., Rossi, J., Pleumeekers, J., … Joyner, C. (2013). From Visible Light-Emitting Diodes to Large-Scale III–V Photonic Integrated Circuits. Proceedings of the IEEE, 101(10), 2255-2270. doi:10.1109/jproc.2013.2275018Hochberg, M., & Baehr-Jones, T. (2010). Towards fabless silicon photonics. Nature Photonics, 4(8), 492-494. doi:10.1038/nphoton.2010.172Bogaerts, W., Fiers, M., & Dumon, P. (2014). Design Challenges in Silicon Photonics. IEEE Journal of Selected Topics in Quantum Electronics, 20(4), 1-8. doi:10.1109/jstqe.2013.2295882Soref, R. (2006). The Past, Present, and Future of Silicon Photonics. IEEE Journal of Selected Topics in Quantum Electronics, 12(6), 1678-1687. doi:10.1109/jstqe.2006.883151Chrostowski, L., & Hochberg, M. (2015). Silicon Photonics Design. doi:10.1017/cbo9781316084168Heck, M. J. R., Bauters, J. F., Davenport, M. L., Doylend, J. K., Jain, S., Kurczveil, G., … Bowers, J. E. (2013). Hybrid Silicon Photonic Integrated Circuit Technology. IEEE Journal of Selected Topics in Quantum Electronics, 19(4), 6100117-6100117. doi:10.1109/jstqe.2012.2235413Keyvaninia, S., Muneeb, M., Stanković, S., Van Veldhoven, P. J., Van Thourhout, D., & Roelkens, G. (2012). Ultra-thin DVS-BCB adhesive bonding of III-V wafers, dies and multiple dies to a patterned silicon-on-insulator substrate. Optical Materials Express, 3(1), 35. doi:10.1364/ome.3.000035Heideman, R., Hoekman, M., & Schreuder, E. (2012). TriPleX-Based Integrated Optical Ring Resonators for Lab-on-a-Chip and Environmental Detection. IEEE Journal of Selected Topics in Quantum Electronics, 18(5), 1583-1596. doi:10.1109/jstqe.2012.2188382Roeloffzen, C. G. H., Zhuang, L., Taddei, C., Leinse, A., Heideman, R. G., van Dijk, P. W. L., … Boller, K.-J. (2013). Silicon nitride microwave photonic circuits. Optics Express, 21(19), 22937. doi:10.1364/oe.21.022937Corbett, B., Loi, R., Zhou, W., Liu, D., & Ma, Z. (2017). Transfer print techniques for heterogeneous integration of photonic components. Progress in Quantum Electronics, 52, 1-17. doi:10.1016/j.pquantelec.2017.01.001Van der Tol, J. J. G. M., Jiao, Y., Shen, L., Millan-Mejia, A., Pogoretskii, V., van Engelen, J. P., & Smit, M. K. (2018). Indium Phosphide Integrated Photonics in Membranes. IEEE Journal of Selected Topics in Quantum Electronics, 24(1), 1-9. doi:10.1109/jstqe.2017.2772786Bachmann, M., Besse, P. A., & Melchior, H. (1994). General self-imaging properties in N × N multimode interference couplers including phase relations. Applied Optics, 33(18), 3905. doi:10.1364/ao.33.003905Soldano, L. B., & Pennings, E. C. M. (1995). Optical multi-mode interference devices based on self-imaging: principles and applications. Journal of Lightwave Technology, 13(4), 615-627. doi:10.1109/50.372474Madsen, C. K., & Zhao, J. H. (1999). Optical Filter Design and Analysis. Wiley Series in Microwave and Optical Engineering. doi:10.1002/0471213756Desurvire, E. (2009). Classical and Quantum Information Theory. doi:10.1017/cbo9780511803758Knill, E., Laflamme, R., & Milburn, G. J. (2001). A scheme for efficient quantum computation with linear optics. Nature, 409(6816), 46-52. doi:10.1038/35051009Capmany, J., & Pérez, D. (2020). Programmable Integrated Photonics. doi:10.1093/oso/9780198844402.001.0001Spagnolo, N., Vitelli, C., Bentivegna, M., Brod, D. J., Crespi, A., Flamini, F., … Sciarrino, F. (2014). Experimental validation of photonic boson sampling. Nature Photonics, 8(8), 615-620. doi:10.1038/nphoton.2014.135Mennea, P. L., Clements, W. R., Smith, D. H., Gates, J. C., Metcalf, B. J., Bannerman, R. H. S., … Smith, P. G. R. (2018). Modular linear optical circuits. Optica, 5(9), 1087. doi:10.1364/optica.5.001087Perez-Lopez, D., Sanchez, E., & Capmany, J. (2018). Programmable True Time Delay Lines Using Integrated Waveguide Meshes. Journal of Lightwave Technology, 36(19), 4591-4601. doi:10.1109/jlt.2018.2831008Pérez-López, D., Gutierrez, A. M., Sánchez, E., DasMahapatra, P., & Capmany, J. (2019). Integrated photonic tunable basic units using dual-drive directional couplers. Optics Express, 27(26), 38071. doi:10.1364/oe.27.038071Jinguji, K., & Kawachi, M. (1995). Synthesis of coherent two-port lattice-form optical delay-line circuit. Journal of Lightwave Technology, 13(1), 73-82. doi:10.1109/50.350643Mookherjea, S., & Yariv, A. (2002). Coupled resonator optical waveguides. IEEE Journal of Selected Topics in Quantum Electronics, 8(3), 448-456. doi:10.1109/jstqe.2002.1016347Heebner, J. E., Chak, P., Pereira, S., Sipe, J. E., & Boyd, R. W. (2004). Distributed and localized feedback in microresonator sequences for linear and nonlinear optics. Journal of the Optical Society of America B, 21(10), 1818. doi:10.1364/josab.21.001818Fandiño, J. S., Muñoz, P., Doménech, D., & Capmany, J. (2016). A monolithic integrated photonic microwave filter. Nature Photonics, 11(2), 124-129. doi:10.1038/nphoton.2016.233Miller, D. A. B. (2012). All linear optical devices are mode converters. Optics Express, 20(21), 23985. doi:10.1364/oe.20.023985Brown, S. D., Francis, R. J., Rose, J., & Vranesic, Z. G. (1992). Field-Programmable Gate Arrays. doi:10.1007/978-1-4615-3572-0Lee, E. K. F., & Gulak, P. G. (1992). Field programmable analogue array based on MOSFET transconductors. Electronics Letters, 28(1), 28-29. doi:10.1049/el:19920017Lee, E. K. F., & Gulak, P. G. (s. f.). A transconductor-based field-programmable analog array. Proceedings ISSCC ’95 - International Solid-State Circuits Conference. doi:10.1109/isscc.1995.535521Pérez, D., Gasulla, I., & Capmany, J. (2018). Field-programmable photonic arrays. Optics Express, 26(21), 27265. doi:10.1364/oe.26.027265Zheng, D., Doménech, J. D., Pan, W., Zou, X., Yan, L., & Pérez, D. (2019). Low-loss broadband 5  ×  5 non-blocking Si3N4 optical switch matrix. Optics Letters, 44(11), 2629. doi:10.1364/ol.44.002629Densmore, A., Janz, S., Ma, R., Schmid, J. H., Xu, D.-X., Delâge, A., … Cheben, P. (2009). Compact and low power thermo-optic switch using folded silicon waveguides. Optics Express, 17(13), 10457. doi:10.1364/oe.17.010457Song, M., Long, C. M., Wu, R., Seo, D., Leaird, D. E., & Weiner, A. M. (2011). Reconfigurable and Tunable Flat-Top Microwave Photonic Filters Utilizing Optical Frequency Combs. IEEE Photonics Technology Letters, 23(21), 1618-1620. doi:10.1109/lpt.2011.2165209Rudé, M., Pello, J., Simpson, R. E., Osmond, J., Roelkens, G., van der Tol, J. J. G. M., & Pruneri, V. (2013). Optical switching at 1.55 μm in silicon racetrack resonators using phase change materials. Applied Physics Letters, 103(14), 141119. doi:10.1063/1.4824714Zheng, J., Khanolkar, A., Xu, P., Colburn, S., Deshmukh, S., Myers, J., … Majumdar, A. (2018). GST-on-silicon hybrid nanophotonic integrated circuits: a non-volatile quasi-continuously reprogrammable platform. Optical Materials Express, 8(6), 1551. doi:10.1364/ome.8.001551Edinger, P., Errando-Herranz, C., & Gylfason, K. B. (2019). Low-Loss MEMS Phase Shifter for Large Scale Reconfigurable Silicon Photonics. 2019 IEEE 32nd International Conference on Micro Electro Mechanical Systems (MEMS). doi:10.1109/memsys.2019.8870616Carroll, L., Lee, J.-S., Scarcella, C., Gradkowski, K., Duperron, M., Lu, H., … O’Brien, P. (2016). Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices. Applied Sciences, 6(12), 426. doi:10.3390/app6120426Bahadori, M., Gazman, A., Janosik, N., Rumley, S., Zhu, Z., Polster, R., … Bergman, K. (2018). Thermal Rectification of Integrated Microheaters for Microring Resonators in Silicon Photonics Platform. Journal of Lightwave Technology, 36(3), 773-788. doi:10.1109/jlt.2017.2781131Cocorullo, G., Della Corte, F. G., Rendina, I., & Sarro, P. M. (1998). Thermo-optic effect exploitation in silicon microstructures. Sensors and Actuators A: Physical, 71(1-2), 19-26. doi:10.1016/s0924-4247(98)00168-xZecevic, N., Hofbauer, M., & Zimmermann, H. (2015). Integrated Pulsewidth Modulation Control for a Scalable Optical Switch Matrix. IEEE Photonics Journal, 7(6), 1-7. doi:10.1109/jphot.2015.2506153Seok, T. J., Quack, N., Han, S., & Wu, M. C. (2015). 50×50 Digital Silicon Photonic Switches with MEMS-Actuated Adiabatic Couplers. Optical Fiber Communication Conference. doi:10.1364/ofc.2015.m2b.4Zortman, W. A., Trotter, D. C., & Watts, M. R. (2010). Silicon photonics manufacturing. Optics Express, 18(23), 23598. doi:10.1364/oe.18.023598Mower, J., Harris, N. C., Steinbrecher, G. R., Lahini, Y., & Englund, D. (2015). High-fidelity quantum state evolution in imperfect photonic integrated circuits. Physical Review A, 92(3). doi:10.1103/physreva.92.032322Pérez, D., & Capmany, J. (2019). Scalable analysis for arbitrary photonic integrated waveguide meshes. Optica, 6(1), 19. doi:10.1364/optica.6.000019Oton, C. J., Manganelli, C., Bontempi, F., Fournier, M., Fowler, D., & Kopp, C. (2016). Silicon photonic waveguide metrology using Mach-Zehnder interferometers. Optics Express, 24(6), 6265. doi:10.1364/oe.24.006265Chen, X., & Bogaerts, W. (2019). A Graph-based Design and Programming Strategy for Reconfigurable Photonic Circuits. 2019 IEEE Photonics Society Summer Topical Meeting Series (SUM). doi:10.1109/phosst.2019.8795068Zibar, D., Wymeersch, H., & Lyubomirsky, I. (2017). Machine learning under the spotlight. Nature Photonics, 11(12), 749-751. doi:10.1038/s41566-017-0058-3Lopez, D. P. (2020). Programmable Integrated Silicon Photonics Waveguide Meshes: Optimized Designs and Control Algorithms. IEEE Journal of Selected Topics in Quantum Electronics, 26(2), 1-12. doi:10.1109/jstqe.2019.2948048Harris, N. C., Bunandar, D., Pant, M., Steinbrecher, G. R., Mower, J., Prabhu, M., … Englund, D. (2016). Large-scale quantum photonic circuits in silicon. Nanophotonics, 5(3), 456-468. doi:10.1515/nanoph-2015-0146Spring, J. B., Metcalf, B. J., Humphreys, P. C., Kolthammer, W. S., Jin, X.-M., Barbieri, M., … Walmsley, I. A. (2012). Boson Sampling on a Photonic Chip. Science, 339(6121), 798-801. doi:10.1126/science.1231692O’Brien, J. L., Furusawa, A., & Vučković, J. (2009). Photonic quantum technologies. Nature Photonics, 3(12), 687-695. doi:10.1038/nphoton.2009.229Kok, P., Munro, W. J., Nemoto, K., Ralph, T. C., Dowling, J. P., & Milburn, G. J. (2007). Linear optical quantum computing with photonic qubits. Reviews of Modern Physics, 79(1), 135-174. doi:10.1103/revmodphys.79.135Politi, A., Cryan, M. J., Rarity, J. G., Yu, S., & O’Brien, J. L. (2008). Silica-on-Silicon Waveguide Quantum Circuits. Science, 320(5876), 646-649. doi:10.1126/science.1155441Politi, A., Matthews, J., Thompson, M. G., & O’Brien, J. L. (2009). Integrated Quantum Photonics. IEEE Journal of Selected Topics in Quantum Electronics, 15(6), 1673-1684. doi:10.1109/jstqe.2009.2026060Thompson, M. G., Politi, A., Matthews, J. C. F., & O’Brien, J. L. (2011). Integrated waveguide circuits for optical quantum computing. IET Circuits, Devices & Systems, 5(2), 94. doi:10.1049/iet-cds.2010.0108Silverstone, J. W., Bonneau, D., O’Brien, J. L., & Thompson, M. G. (2016). Silicon Quantum Photonics. IEEE Journal of Selected Topics in Quantum Electronics, 22(6), 390-402. doi:10.1109/jstqe.2016.2573218Poot, M., Schuck, C., Ma, X., Guo, X., & Tang, H. X. (2016). Design and characterization of integrated components for SiN photonic quantum circuits. Optics Express, 24(7), 6843. doi:10.1364/oe.24.006843Saleh, M. F., Di Giuseppe, G., Saleh, B. E. A., & Teich, M. C. (2010). Modal and polarization qubits in Ti:LiNbO_3 photonic circuits for a universal quantum logic gate. Optics Express, 18(19), 20475. doi:10.1364/oe.18.020475Harris, N. C., Carolan, J., Bunandar, D., Prabhu, M., Hochberg, M., Baehr-Jones, T., … Englund, D. (2018). Linear programmable nanophotonic processors. Optica, 5(12), 1623. doi:10.1364/optica.5.001623Qiang, X., Zhou, X., Wang, J., Wilkes, C. M., Loke, T., O’Gara, S., … Matthews, J. C. F. (2018). Large-scale silicon quantum photonics implementing arbitrary two-qubit processing. Nature Photonics, 12(9), 534-539. doi:10.1038/s41566-018-0236-yLee, B. G., & Dupuis, N. (2019). Silicon Photonic Switch Fabrics: Technology and Architecture. Journal of Lightwave Technology, 37(1), 6-20. doi:10.1109/jlt.2018.2876828Cheng, Q., Rumley, S., Bahadori, M., & Bergman, K. (2018). Photonic switching in high performance datacenters [Invited]. Optics Express, 26(12), 16022. doi:10.1364/oe.26.016022Wonfor, A., Wang, H., Penty, R. V., & White, I. H. (2011). Large Port Count High-Speed Optical Switch Fabric for Use Within Datacenters [Invited]. Journal of Optical Communications and Networking, 3(8), A32. doi:10.1364/jocn.3.000a32Hamamoto, K., Anan, T., Komatsu, K., Sugimoto, M., & Mito, I. (1992). First 8×8 semiconductor optical matrix switches using GaAs/AlGaAs electro-optic guided-wave directional couplers. Electronics Letters, 28(5), 441. doi:10.1049/el:19920278Van Campenhout, J., Green, W. M., Assefa, S., & Vlasov, Y. A. (2009). Low-power, 2×2 silicon electro-optic switch with 110-nm bandwidth for broadband reconfigurable optical networks. Optics Express, 17(26), 24020. doi:10.1364/oe.17.024020Dupuis, N., Lee, B. G., Rylyakov, A. V., Kuchta, D. M., Baks, C. W., Orcutt, J. S., … Schow, C. L. (2015). D