Integral optimization of spare parts inventories in systems with redundancies

In this paper, we analyze spare parts supply for a system with a "k-out-of-N" redundancy structure for key components, different standby policies (cold, warm and hot standby redundancy) and local spare parts inventories for sub-components. We assume multiple part types (sub-components) that fail randomly with exponentially distributed interfailure times. Due to the standby policies and the limited number of installed components, the total failure rate depends on the state of the system. Replacement times and stock replenishment times are also assumed to be exponentially distributed and depend on the part types. We present an exact method together with a simple and effi�cient approximation scheme for the evaluation of the system availability given certain stock levels. The proposed approximation is further used in a simple optimization heuristic to demonstrate how the total system costs can be reduced if the redundancy structure is optimized while taking into account the local stock of the spare parts. The presented numerical results clearly show the importance of the local inventories with spares even in the systems with redundancies

A study of the selection of microcomputer architectures to automate planetary spacecraft power systems

Performance and reliability models of alternate microcomputer architectures as a methodology for optimizing system design were examined. A methodology for selecting an optimum microcomputer architecture for autonomous operation of planetary spacecraft power systems was developed. Various microcomputer system architectures are analyzed to determine their application to spacecraft power systems. It is suggested that no standardization formula or common set of guidelines exists which provides an optimum configuration for a given set of specifications

A coloured Petri net framework for modelling aircraft fleet maintenance

The aircraft fleet maintenance organisation is responsible for keeping aircraft in a safe, efficient operating condition. Through optimising the use of maintenance resources and the implementation of maintenance activities, fleet maintenance management aims to maximise fleet performance by, for example, ensuring there is minimal deviation from the planned operational schedule,that the number of unexpected failures is minimised or that maintenance cost is kept at a minimum. To obtain overall fleet performance, the performance of individual aircraft must first be known. The calculation of aircraft performance requires an accurate model of the fleet operation and maintenance processes. This paper aims to introduce a framework that can be used to build aircraft fleet maintenance models. A variety of CPN (coloured Petri nets) models are established to represent fleet maintenance activities and maintenance management, as well as the factors that have a significant impact on fleet maintenance including fleet operation, aircraft failure logic and component failure processes. Such CPN models provide an ideal structured framework for Monte Carlo simulation analysis, within which calculations can be performed in order to determine numerous fleet reliability and maintenance performance measures

A general graphical user interface for automatic reliability modeling

Reported here is a general Graphical User Interface (GUI) for automatic reliability modeling of Processor Memory Switch (PMS) structures using a Markov model. This GUI is based on a hierarchy of windows. One window has graphical editing capabilities for specifying the system's communication structure, hierarchy, reconfiguration capabilities, and requirements. Other windows have field texts, popup menus, and buttons for specifying parameters and selecting actions. An example application of the GUI is given

Fault-tolerant computer study

A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed

Mars spacecraft power system development Interim report

Modified Mariner power system design for Mars mission

A Survey of Fault-Tolerance Techniques for Embedded Systems from the Perspective of Power, Energy, and Thermal Issues

The relentless technology scaling has provided a significant increase in processor performance, but on the other hand, it has led to adverse impacts on system reliability. In particular, technology scaling increases the processor susceptibility to radiation-induced transient faults. Moreover, technology scaling with the discontinuation of Dennard scaling increases the power densities, thereby temperatures, on the chip. High temperature, in turn, accelerates transistor aging mechanisms, which may ultimately lead to permanent faults on the chip. To assure a reliable system operation, despite these potential reliability concerns, fault-tolerance techniques have emerged. Specifically, fault-tolerance techniques employ some kind of redundancies to satisfy specific reliability requirements. However, the integration of fault-tolerance techniques into real-time embedded systems complicates preserving timing constraints. As a remedy, many task mapping/scheduling policies have been proposed to consider the integration of fault-tolerance techniques and enforce both timing and reliability guarantees for real-time embedded systems. More advanced techniques aim additionally at minimizing power and energy while at the same time satisfying timing and reliability constraints. Recently, some scheduling techniques have started to tackle a new challenge, which is the temperature increase induced by employing fault-tolerance techniques. These emerging techniques aim at satisfying temperature constraints besides timing and reliability constraints. This paper provides an in-depth survey of the emerging research efforts that exploit fault-tolerance techniques while considering timing, power/energy, and temperature from the real-time embedded systems’ design perspective. In particular, the task mapping/scheduling policies for fault-tolerance real-time embedded systems are reviewed and classified according to their considered goals and constraints. Moreover, the employed fault-tolerance techniques, application models, and hardware models are considered as additional dimensions of the presented classification. Lastly, this survey gives deep insights into the main achievements and shortcomings of the existing approaches and highlights the most promising ones

Advanced information processing system: The Army fault tolerant architecture conceptual study. Volume 2: Army fault tolerant architecture design and analysis

Described here is the Army Fault Tolerant Architecture (AFTA) hardware architecture and components and the operating system. The architectural and operational theory of the AFTA Fault Tolerant Data Bus is discussed. The test and maintenance strategy developed for use in fielded AFTA installations is presented. An approach to be used in reducing the probability of AFTA failure due to common mode faults is described. Analytical models for AFTA performance, reliability, availability, life cycle cost, weight, power, and volume are developed. An approach is presented for using VHSIC Hardware Description Language (VHDL) to describe and design AFTA's developmental hardware. A plan is described for verifying and validating key AFTA concepts during the Dem/Val phase. Analytical models and partial mission requirements are used to generate AFTA configurations for the TF/TA/NOE and Ground Vehicle missions