41,679 research outputs found

    Integration and verification of parameterized register interfaces

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    Abstract. This thesis takes an in-depth look on parameterized register models, their generation and use. The aim is to discover improvements to the current method of generating parameterized register models. The thesis is divided into two halves: a practical section that consists of a study on the generation of parameterized register models, and a theory section that supports the topics gone over in the practical section. The practical section studied the generation flow and tools currently used at Nordic Semiconductor. The flow was analyzed to discover changes that would enable the generation of more flexible parameterized register models. The suggested changes were then used to generate a dynamic register model for a highly configurable intellectual property (IP) core. The register model was validated using a register test sequence and functional tests. Finally, the functionality of the generated register model was compared to a manually implemented model. In the end, the test sequences and functional tests passed without errors. The generated register model could be configured directly from the testbench without editing the model manually. This also meant that the applied configurations would not be lost even if the register model were to be regenerated. The resulting register model was significantly more flexible than the previous generated models.Parametrisoitujen rekisterirajapintojen integrointi ja verifiointi. Tiivistelmä. Tässä opinnäytetyössä tutustutaan parametrisoituihin rekisterimalleihin, niiden generointiin, ja niiden käyttöön. Tavoitteena on löytää parannuksia nykyiseen parametrisoitujen rekisterimallien generointitapaan. Opinnäytetyö on jaettu kahteen puoliskoon: käytännön osuuteen, joka koostuu parametrisoitujen rekisterimallien tutkimuksesta, ja teoreettisesta osuudesta, joka tukee käytännön osuudessa käsiteltyjä aiheita. Käytännön osuus tutki Nordic Semiconductorilla tällä hetkellä rekisterimallin generointiin käytettyjä prosesseja ja työkaluja. Niitä analysoimalla pyrittiin löytämään muutoksia, joiden avulla voisi generoida joustavampia parametrisoituja rekisterimalleja. Kyseisten muutosten avulla generoitiin sitten dynaaminen rekisterimalli IP lohkolle, joka sisältää paljon konfiguroitavia parametrejä. Generoitu malli varmennettiin rekisterien testisekvenssillä ja toiminnallisilla testeillä. Lopuksi rekisterimallin toiminnallisuutta verrattiin käsin kirjoitetun rekisterimallin toiminnallisuuteen. Testisekvenssi ja toiminnalliset testit läpäistiin simuloinnissa lopulta ilman virheitä. Generoitu rekisterimalli oli konfiguroitavissa suoraan testipenkistä, eikä sitä tarvinnut muokata manuaalisesti. Tämä tarkoitti myös sitä, että testipenkissä asetettuja konfiguraatioita ei menetetä, jos rekisterimalli generoidaan uudelleen. Lopullinen rekisterimalli oli merkittävästi joustavampi kuin aikaisemmat generoidut mallit

    From FPGA to ASIC: A RISC-V processor experience

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    This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

    A High-level Methodology for Automatically Generating Dynamic Partially Reconfigurable Systems using IP-XACT and the UML MARTE Profile

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    International audienceDynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building com- plex systems remains a daunting task. Recently, approaches based on Model-Driven Engi- neering (MDE) and UML MARTE standard have emerged which aim to simplify the design of complex SoCs, and in some cases, DPR systems. Nevertheless, many of these approaches lacked a standard intermediate representation to pass from high-levels of descriptions to ex- ecutable models. However, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. We present the MARTE modeling concepts and how these models are mapped to IP-XACT objects; the emphasis is given to the generation of IP cores that can be used in the Xilinx EDK (Embedded Design Kit) environment, since we aim to develop a complete flow around their Dynamic Partial Reconfiguration design flow. Finally, we present a case study integrating the presented concepts, showing the benefits in design efforts compared with a purely VHDL approach and using solely EDK. Experimental results show a reduction of the design efforts required to obtain the netlist required for the DPR design flow from hours required in VHDL and Xilinx EDK, to less the one hour and minutes for IP integration

    Pcie Ip Validation Process Across Process Corner, Voltage And Temperature Conditions

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    IP validation has become more challenging for FPGA device as it supports high operating speed. The Peripheral Component Interconnect Express (PCIe) is an IP used for high speed data transfer that supported by Intel FPGAs. The base specifications of PCIe 3.0 supports 8.0 GT/s, 5.0 GT/s and 2.5 GT/s. The link training and Initialization takes place at physical layer to initialize the link width and link data rate. The physical layer is getting more complex when it supports higher speed. The operational state only happens when Link Training and Status State Machine (LTSSM) reaches L0 state after device being configured. The stability of link training is improved by optimizing the soft logic design in application layer. Two protocol tests usually validated in industry are link up testing and link & higher layer testing. Debugging tools supported by Quartus are fully utilized to detect any failure during link training. The characterization of link performance covers process corners, voltage and temperature conditions are hard to analyze. By using hypothesis testing method, data collected gives a clear trend on the PCIe link performance. The H0 statement shows a significant difference for passing and failing case. In this research, the worst case happened at low voltage and low temperature regardless of any process corners. The p-value is greater than 0.05 proved H0 statement is accepted. The difference on passing and failing percentage is insignificantly impacting overall link performance of PCIe. It concludes that the bug is random and not caused by any defects on the silicon layout of FPGA device. Thus, IP validation shows the robustness of the device and able to comply with base specification of PCIe

    Feasibility study of an Integrated Program for Aerospace vehicle Design (IPAD). Volume 1B: Concise review

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    Reports on the design process, support of the design process, IPAD System design catalog of IPAD technical program elements, IPAD System development and operation, and IPAD benefits and impact are concisely reviewed. The approach used to define the design is described. Major activities performed during the product development cycle are identified. The computer system requirements necessary to support the design process are given as computational requirements of the host system, technical program elements and system features. The IPAD computer system design is presented as concepts, a functional description and an organizational diagram of its major components. The cost and schedules and a three phase plan for IPAD implementation are presented. The benefits and impact of IPAD technology are discussed

    A NASA family of minicomputer systems, Appendix A

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    This investigation was undertaken to establish sufficient specifications, or standards, for minicomputer hardware and software to provide NASA with realizable economics in quantity purchases, interchangeability of minicomputers, software, storage and peripherals, and a uniformly high quality. The standards will define minicomputer system component types, each specialized to its intended NASA application, in as many levels of capacity as required

    An Ontology-Based Recommender System with an Application to the Star Trek Television Franchise

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    Collaborative filtering based recommender systems have proven to be extremely successful in settings where user preference data on items is abundant. However, collaborative filtering algorithms are hindered by their weakness against the item cold-start problem and general lack of interpretability. Ontology-based recommender systems exploit hierarchical organizations of users and items to enhance browsing, recommendation, and profile construction. While ontology-based approaches address the shortcomings of their collaborative filtering counterparts, ontological organizations of items can be difficult to obtain for items that mostly belong to the same category (e.g., television series episodes). In this paper, we present an ontology-based recommender system that integrates the knowledge represented in a large ontology of literary themes to produce fiction content recommendations. The main novelty of this work is an ontology-based method for computing similarities between items and its integration with the classical Item-KNN (K-nearest neighbors) algorithm. As a study case, we evaluated the proposed method against other approaches by performing the classical rating prediction task on a collection of Star Trek television series episodes in an item cold-start scenario. This transverse evaluation provides insights into the utility of different information resources and methods for the initial stages of recommender system development. We found our proposed method to be a convenient alternative to collaborative filtering approaches for collections of mostly similar items, particularly when other content-based approaches are not applicable or otherwise unavailable. Aside from the new methods, this paper contributes a testbed for future research and an online framework to collaboratively extend the ontology of literary themes to cover other narrative content.Comment: 25 pages, 6 figures, 5 tables, minor revision

    An Analysis of Applications Development Systems for Remotely Sensed, Multispectral Data for the Earth Observations Division of the NASA Lyndon B. Johnson Space Center

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    An application development system (ADS) is examined for remotely sensed, multispectral data at the Earth Observations Division (EOD) at Johnson Space Center. Design goals are detailed, along with design objectives that an ideal system should contain. The design objectives were arranged according to the priorities of EOD's program objectives. Four systems available to EOD were then measured against the ideal ADS as defined by the design objectives and their associated priorities. This was accomplished by rating each of the systems on each of the design objectives. Utilizing the established priorities, it was determined how each system stood up as an ADS. Recommendations were made as to possible courses of action for EOD to pursue to obtain a more efficient ADS

    System configuration and executive requirements specifications for reusable shuttle and space station/base

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    System configuration and executive requirements specifications for reusable shuttle and space station/bas
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