Spacecraft attitude control using a smart control system

Traditionally, spacecraft attitude control has been implemented using control loops written in native code for a space hardened processor. The Naval Research Lab has taken this approach during the development of the Attitude Control Electronics (ACE) package. After the system was developed and delivered, NRL decided to explore alternate technologies to accomplish this same task more efficiently. The approach taken by NRL was to implement the ACE control loops using systems technologies. The purpose of this effort was to: (1) research capabilities required of an expert system in processing a classic closed-loop control algorithm; (2) research the development environment required to design and test an embedded expert systems environment; (3) research the complexity of design and development of expert systems versus a conventional approach; and (4) test the resulting systems against the flight acceptance test software for both response and accuracy. Two expert systems were selected to implement the control loops. Criteria used for the selection of the expert systems included that they had to run in both embedded systems and ground based environments. Using two different expert systems allowed a comparison of the real-time capabilities, inferencing capabilities, and the ground-based development environment. The two expert systems chosen for the evaluation were Spacecraft Command Language (SCL), and NEXTPERT Object. SCL is a smart control system produced for the NRL by Interface and Control Systems (ICS). SCL was developed to be used for real-time command, control, and monitoring of a new generation of spacecraft. NEXPERT Object is a commercially available product developed by Neuron Data. Results of the effort were evaluated using the ACE test bed. The ACE test bed had been developed and used to test the original flight hardware and software using simulators and flight-like interfaces. The test bed was used for testing the expert systems in a 'near-flight' environment. The technical approach, the system architecture, the development environments, knowledge base development, and results of this effort are detailed

Software systems for operation, control, and monitoring of the EBEX instrument

We present the hardware and software systems implementing autonomous operation, distributed real-time monitoring, and control for the EBEX instrument. EBEX is a NASA-funded balloon-borne microwave polarimeter designed for a 14 day Antarctic flight that circumnavigates the pole. To meet its science goals the EBEX instrument autonomously executes several tasks in parallel: it collects attitude data and maintains pointing control in order to adhere to an observing schedule; tunes and operates up to 1920 TES bolometers and 120 SQUID amplifiers controlled by as many as 30 embedded computers; coordinates and dispatches jobs across an onboard computer network to manage this detector readout system; logs over 3~GiB/hour of science and housekeeping data to an onboard disk storage array; responds to a variety of commands and exogenous events; and downlinks multiple heterogeneous data streams representing a selected subset of the total logged data. Most of the systems implementing these functions have been tested during a recent engineering flight of the payload, and have proven to meet the target requirements. The EBEX ground segment couples uplink and downlink hardware to a client-server software stack, enabling real-time monitoring and command responsibility to be distributed across the public internet or other standard computer networks. Using the emerging dirfile standard as a uniform intermediate data format, a variety of front end programs provide access to different components and views of the downlinked data products. This distributed architecture was demonstrated operating across multiple widely dispersed sites prior to and during the EBEX engineering flight.Comment: 11 pages, to appear in Proceedings of SPIE Astronomical Telescopes and Instrumentation 2010; adjusted metadata for arXiv submissio

HW/SW Co-design and Prototyping Approach for Embedded Smart Camera: ADAS Case Study

In 1968, Volkswagen integrated an electronic circuit as a new control fuel injection system, called the “Little Black Box”, it is considered as the first embedded system in the automotive industry. Currently, automobile constructors integrate several embedded systems into any of their new model vehicles. Behind these automobile’s electronics systems, a sophisticated Hardware/Software (HW/SW) architecture, which is based on heterogeneous components, and multiple CPUs is built. At present, they are more oriented toward visionbased systems using tiny embedded smart camera. This visionbased system in real time aspects represents one of the most challenging issues, especially in the domain of automobile’s applications. On the design side, one of the optimal solutions adopted by embedded systems designer for system performance, is to associate CPUs and hardware accelerators in the same design, in order to reduce the computational burden on the CPU and to speed-up the data processing. In this paper, we present a hardware platform-based design approach for fast embedded smart Advanced Driver Assistant System (ADAS) design and prototyping, as an alternative for the pure time-consuming simulation technique. Based on a Multi-CPU/FPGA platform, we introduced a new methodology/flow to design the different HW and SW parts of the ADAS system. Then, we shared our experience in designing and prototyping a HW/SW vision based on smart embedded system as an ADAS that helps to increase the safety of car’s drivers. We presented a real HW/SW prototype of the vision ADAS based on a Zynq FPGA. The system detects the fatigue/drowsiness state of the driver by monitoring the eyes closure and generates a real time alert. A new HW Skin Segmentation step to locate the eyes/face is proposed. Our new approach migrates the skin segmentation step from processing system (SW) to programmable logic (HW) taking the advantage of High-Level Synthesis (HLS) tool flow to accelerate the implementation, and the prototyping of the Vision based ADAS on a hardware platform

Employment of Real-Time/FPGA Architectures for Test and Control of Automotive Engines

Nowadays the production of increasingly complex and electrified vehicles requires the implementation of new control and monitoring systems. This reason, together with the tendency of moving rapidly from the test bench to the vehicle, leads to a landscape that requires the development of embedded hardware and software to face the application effectively and efficiently. The development of application-based software on real-time/FPGA hardware could be a good answer for these challenges: FPGA grants parallel low-level and high-speed calculation/timing, while the Real-Time processor can handle high-level calculation layers, logging and communication functions with determinism. Thanks to the software flexibility and small dimensions, these architectures can find a perfect collocation as engine RCP (Rapid Control Prototyping) units and as smart data logger/analyser, both for test bench and on vehicle application. Efforts have been done for building a base architecture with common functionalities capable of easily hosting application-specific control code. Several case studies originating in this scenario will be shown; dedicated solutions for protype applications have been developed exploiting a real-time/FPGA architecture as ECU (Engine Control Unit) and custom RCP functionalities, such as water injection and testing hydraulic brake control

Modeling and analysis of real-time software systems using UML

Real-Time Systems (RTS) should not only function correctly but should also satisfy time constraints. RTS include embedded systems, which are used nowadays in a variety of applications. These are, for instance, house appliances, automotive, aeronautic/aerospace, and health monitoring systems, to mention just a few. The design of such systems is complex and challenging. In order to cope with the complexity of RTS, there is shift in their development to follow a model-driven approach, such as the Model Driven Architecture (MDA), which relies on using models of high level of abstraction. The Unified Modeling Language (UML) is the Object Management Group (OMG) standard modeling language to support MDA. UML is appropriate for software systems because it allows for a multi-view modeling approach through its multitude of diagrams covering the structure, the behavior and the deployment architecture. Moreover, UML is also used in the domain of real-time software systems. This is achieved through its profiles, including, the OMG standard profile for Schedulability, Performance and Time (UML/SPT) or the upcoming standard UML Profile for Modeling and Analysis of Real-Time and Embedded Systems (MARTE). However, UML modeling faces some challenging issues such as model consistency. This issue becomes worse in the context of real-time software systems because additional aspects should be taken into consideration, including time, concurrency and schedulability. In this thesis, we address several issues related to modeling and validation of RTS with UML. We focus in particular on the consistency of UML/SPT models. We adopt an incremental approach to check the consistency of these models by distinguishing the syntactic and semantic levels. The latter is further decomposed into behavioral, concurrency-related and time consistency. Our contributions in this thesis are fourfold. First, we leverage the extensibility mechanisms of UML to propose an extension to UML/SPT. This extension enables the modeling of multicast communications, which is required for the description of the behavior of certain real-time protocols. Second, we propose a formalization of the concurrency modeling capability in UML/SPT using timed automata. This formal semantics allows for applying well-established model checking techniques to check concurrency related consistency in UML/SPT models. Third, we propose an MDA-compliant approach to enable schedulability analysis of UML/SPT models. We present a proof of concept for this approach through a prototype implementation using the Atlas Transformation Language (ATL) and XML-based technologies. Finally, we use the schedulability analysis applied to UML/SPT models in order to check the time consistency of a system design modeled by means of a set of state machines with respect to time constraints modeled using a set of sequence diagrams annotated with UML/SPT time stereotypes. Keywords : Real-time systems, Model-driven Architecture, UML, UML/SPT, Model transformation, ATL, XML, XSLT, Consistency, Concurrency, Model Checking, Schedulability Analysis

Contract Aware Components, 10 years after

The notion of contract aware components has been published roughly ten years ago and is now becoming mainstream in several fields where the usage of software components is seen as critical. The goal of this paper is to survey domains such as Embedded Systems or Service Oriented Architecture where the notion of contract aware components has been influential. For each of these domains we briefly describe what has been done with this idea and we discuss the remaining challenges.Comment: In Proceedings WCSI 2010, arXiv:1010.233

Monitoring Architecture for Real Time Systems

It can be hard to understand how an operating system - and software in general - reached a certain output just by looking at said output. A simple approach is to use loggers, or simple print statements on some specific critical areas, however that is an approach that does not scale very well in a consistent and manageable way. The purpose of this thesis is to propose and develop a tool - a Monitoring Tool - capable of capturing and recording the execution of a given application with minimal intrusion in the context of real-time embedded systems, namely using a space-qualified version of the RTEMS real-time operating system, and making that information available for further processing and analysis. Multicore environments are also considered. The current state of the art in monitoring and execution tracing is presented, featuring both a literature review and a discussion of existing tools and frameworks. Using an implementation of the proposed architecture, the tool was tested in both unicore and multicore configurations in both sparc and arm architectures, and was able to record execution data of a sample application, with varying degrees of verbosity.Nem sempre é fácil perceber como é que um sistema operativo - e software em geral - chegaram a determinado resultado apenas olhando para este. A abordagem normal é usar registos, ou pequenas impressões em locais estratégicos do código, no entanto esta abordagem não é escalável de forma consistente e sustentada. O propósito desta tese é o de propor e desenvolver uma ferramenta - uma ferramenta de monitorização - capaz de capturar e registar a execução de uma dada aplicação com o mínimo de impacto no contexto de sistemas embebidos de tempo-real, nomeadamente usando uma versão do sistema operativo de tempo-real Real-Time Executive for Multiprocessor Systems (RTEMS) qualificada para o espaço, e colocando essa informação à disposição para processamento e análise futura. Ambientes com múltiplos núcleos de processamento são também considerados. O atual estado da arte em monitorização e registo de execução de software é apresentado, destacando tanto exemplos da literatura como ferramentas e frameworks existentes. Usando uma implementação da arquitetura proposta, a ferramenta foi testada em configurações com um ou mais núcleos de processamento em arquiteturas sparc e arm, tendo sido capaz de registar e gravar dados da execução de uma aplicação de exemplo, como vários níveis de detalhe