A Low-Power, Reconfigurable, Pipelined ADC with Automatic Adaptation for Implantable Bioimpedance Applications

Biomedical monitoring systems that observe various physiological parameters or electrochemical reactions typically cannot expect signals with fixed amplitude or frequency as signal properties can vary greatly even among similar biosignals. Furthermore, advancements in biomedical research have resulted in more elaborate biosignal monitoring schemes which allow the continuous acquisition of important patient information. Conventional ADCs with a fixed resolution and sampling rate are not able to adapt to signals with a wide range of variation. As a result, reconfigurable analog-to-digital converters (ADC) have become increasingly more attractive for implantable biosensor systems. These converters are able to change their operable resolution, sampling rate, or both in order convert changing signals with increased power efficiency. Traditionally, biomedical sensing applications were limited to low frequencies. Therefore, much of the research on ADCs for biomedical applications focused on minimizing power consumption with smaller bias currents resulting in low sampling rates. However, recently bioimpedance monitoring has become more popular because of its healthcare possibilities. Bioimpedance monitoring involves injecting an AC current into a biosample and measuring the corresponding voltage drop. The frequency of the injected current greatly affects the amplitude and phase of the voltage drop as biological tissue is comprised of resistive and capacitive elements. For this reason, a full spectrum of measurements from 100 Hz to 10-100 MHz is required to gain a full understanding of the impedance. For this type of implantable biomedical application, the typical low power, low sampling rate analog-to-digital converter is insufficient. A different optimization of power and performance must be achieved. Since SAR ADC power consumption scales heavily with sampling rate, the converters that sample fast enough to be attractive for bioimpedance monitoring do not have a figure-of-merit that is comparable to the slower converters. Therefore, an auto-adapting, reconfigurable pipelined analog-to-digital converter is proposed. The converter can operate with either 8 or 10 bits of resolution and with a sampling rate of 0.1 or 20 MS/s. Additionally, the resolution and sampling rate are automatically determined by the converter itself based on the input signal. This way, power efficiency is increased for input signals of varying frequency and amplitude

Biosensors and CMOS Interface Circuits

abstract: Analysing and measuring of biological or biochemical processes are of utmost importance for medical, biological and biotechnological applications. Point of care diagnostic system, composing of biosensors, have promising applications for providing cheap, accurate and portable diagnosis. Owing to these expanding medical applications and advances made by semiconductor industry biosensors have seen a tremendous growth in the past few decades. Also emergence of microfluidics and non-invasive biosensing applications are other marker propellers. Analyzing biological signals using transducers is difficult due to the challenges in interfacing an electronic system to the biological environment. Detection limit, detection time, dynamic range, specificity to the analyte, sensitivity and reliability of these devices are some of the challenges in developing and integrating these devices. Significant amount of research in the field of biosensors has been focused on improving the design, fabrication process and their integration with microfluidics to address these challenges. This work presents new techniques, design and systems to improve the interface between the electronic system and the biological environment. This dissertation uses CMOS circuit design to improve the reliability of these devices. Also this work addresses the challenges in designing the electronic system used for processing the output of the transducer, which converts biological signal into electronic signal.Dissertation/ThesisM.S. Electrical Engineering 201

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Efficiency Improvement of LDO Output Based Linear Regulator With Supercapacitor Energy Recovery – A versatile new technique with an example of a 5V to 1.5V version

Supercapacitors are used in various industrial applications and the supercapacitors technology is gradually progressing into a mature state. Common applications of supercapacitors are in electric vehicles, hybrid electric vehicles, uninterruptible power supply (UPS) and in portable devices such as cellular phones and laptops. The capacitance values range from fractional Farads to few thousand Farads and their continuos DC voltage ratings are from 2V to 6V. At University of Waikato, a team works on using supercapacitors for improving the efficiency of linear voltage regulators. In particular, this patented technique aims at combining off the shelfs LDO ICs and a supercapacitor array for improving end to end efficiency of linear regulator. My work is aimed at developing the theoretical background and designing prototype circuitry for a voltage regulator for the case of unregulated input supply is more than 3 times of the minimum input voltage requirement of the LDO which is applicable for a 5V to 1.5V regulator. Experimental results are indicated with future suggestions for improvement

Low Voltage Low Power Analogue Circuits Design

Disertační práce je zaměřena na výzkum nejběžnějších metod, které se využívají při návrhu analogových obvodů s využití nízkonapěťových (LV) a nízkopříkonových (LP) struktur. Tyto LV LP obvody mohou být vytvořeny díky vyspělým technologiím nebo také využitím pokročilých technik návrhu. Disertační práce se zabývá právě pokročilými technikami návrhu, především pak nekonvenčními. Mezi tyto techniky patří využití prvků s řízeným substrátem (bulk-driven - BD), s plovoucím hradlem (floating-gate - FG), s kvazi plovoucím hradlem (quasi-floating-gate - QFG), s řízeným substrátem s plovoucím hradlem (bulk-driven floating-gate - BD-FG) a s řízeným substrátem s kvazi plovoucím hradlem (quasi-floating-gate - BD-QFG). Práce je také orientována na možné způsoby implementace známých a moderních aktivních prvků pracujících v napěťovém, proudovém nebo mix-módu. Mezi tyto prvky lze začlenit zesilovače typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za účelem potvrzení funkčnosti a chování výše zmíněných struktur a prvků byly vytvořeny příklady aplikací, které simulují usměrňovací a induktanční vlastnosti diody, dále pak filtry dolní propusti, pásmové propusti a také univerzální filtry. Všechny aktivní prvky a příklady aplikací byly ověřeny pomocí PSpice simulací s využitím parametrů technologie 0,18 m TSMC CMOS. Pro ilustraci přesného a účinného chování struktur je v disertační práci zahrnuto velké množství simulačních výsledků.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the non–conventional ones which are bulk–driven (BD), floating–gate (FG), quasi–floating–gate (QFG), bulk–driven floating–gate (BD–FG) and bulk–driven quasi–floating–gate (BD–QFG) techniques. The thesis also looks at ways of implementing structures of well–known and modern active elements operating in voltage–, current–, and mixed–mode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fully–differential second generation current conveyor (FB–CCII), fully–balanced differential difference amplifier (FB–DDA), voltage differencing transconductance amplifier (VDTA), current–controlled current differencing buffered amplifier (CC–CDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diode–less rectifier and inductance simulations, as well as low–pass, band–pass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.

Circuits and systems for inductive power transfer

Recently, the development of Wireless Power Transfer (WPT) systems has shown to be a key factor for improving the robustness, usability and autonomy of many mobile devices. The WPT link relaxes the trade-off between the battery size and the power availability, enabling highly innovative applications. This thesis aims to develop novel techniques to increase efficiency and operating distance of inductive power transfer systems. We addressed the design of the inductive link and various circuits used in the receiver. Moreover, we performed a careful system-level analysis, taking into account the design of different blocks and their interaction. The analysis is oriented towards the development of low power applications, such as Active Implantable Medical Device (AIMD) or Radio-Frequency Identification (RFID) systems. Three main approaches were considered to increase efficiency and operating distance: 1) The use of additional resonant coils, placed between the transmitter and the receiver. 2) The receiver coil impedance matching. 3) The design of high-efficiency rectifiers and dc-dc converters. The effect of the additional coils in the inductive link is usually studied without considering its influence on other parts of the WPT system. In this work, we theoretically analyzed and compared 2 and 3-coil links, showing the advantages of using the additional coil together with a matching network in the receiver. The effect of the additional coils in a closed-loop regulated system is also addressed, demonstrating that the feedback-loop design should consider the number of coils used in the link. Furthermore, the inclusion of one additional resonant coil in an actual half-duplex RFID system at 134:2 kHz is presented. The maximum efficiency point can be achieved by adjusting the receiver coil load impedance in order to reach its optimum value. In inductive powering, this optimum impedance is often achieved by adapting the input impedance of a dc-dc converter in the receiver. A matching network can also be used for the same purpose, as have been analyzed in previous works. In this thesis, we propose a joint design using both, matching network and dc-dc converters, highlighting the benefits of using the combined approach. A rectifier must be included in any WPT receiver. Usually, a dc-dc converter is included after the rectifier to adjust the output voltage or control the rectifier load impedance. The efficiency of both, rectifier and dc-dc converter, impacts not only the load power but also the receiver dissipation. In applications such as AIMDs, to get the most amount of power with low dissipation is crucial to full safety requirements. We present the design of an active rectifier and a switched capacitor dc-dc converter. In low-power applications, the power consumption of any auxiliary block used in the circuit may decrease the efficiency due to its quiescent consumption. Therefore, we have carefully designed these auxiliary blocks, such as operational transconductance amplifiers and voltage comparators. The main contributions of this thesis are: . Deduction of simplified equations to compare 2 and 3-coil links with an optimized Matching Network (MN). . Development of a 3-coil link half-duplex RFID 134.2 kHz system. . Analysis of the influence of the titanium case in the inductive link of implantable medical devices. . Development of a joint design ow which exploits the advantages of using both MNs and dc-dc converters in the receiver to achieve load impedance matching. . Analysis of closed-loop postregulated systems, highlighting the effects that the additional coils, receiver resonance (series or parallel), and type of driver (voltage or current) used in the transmitter, have in the feedback control loop. . Proposal of systematic analysis and design of charge recycling switches in step-up dc-dc converters. . New architecture for low-power high slew-rate operational transconductance amplifier. Novel architecture for high-efficiency active rectifier. The thesis is essentially based on the publications [1{9]. During the PhD program, other publications were generated [10{15] that are partially or non-included in the thesis. Additionally, some contributions presented in the text, are in process of publication.Hace ya un buen tiempo que las redes inalámbricas constituyen uno de los temas de investigación más estudiados en el área de las telecomunicaciones. Actualmente un gran porcentaje de los esfuerzos de la comunidad científifica y del sector industrial están concentrados en la definición de los requerimientos y estándares de la quinta generación de redes móviles. 5G implicará la integración y adaptación de varias tecnologías, no solo del campo de las telecomunicaciones sino también de la informática y del análisis de datos, con el objetivo de lograr una red lo suficientemente flexible y escalable como para satisfacer los requerimientos para la enorme variedad de casos de uso implicados en el desarrollo de la “sociedad conectada”. Un problema que se presenta en las redes inalámbricas actuales, que por lo tanto genera un desafío más que interesante para lo que se viene, es la escasez de espectro radioeléctrico para poder asignar bandas a nuevas tecnologías y nuevos servicios. El espectro está sobreasignado a los diferentes servicios de telecomunicaciones existentes y las bandas de uso libre o no licenciadas están cada vez más saturadas de equipos que trabajan en ellas (basta pensar lo que sucede en la banda no licenciada de 2.4 GHz). Sin embargo, existen análisis y mediciones que muestran que en diversas zonas y en diversas escalas de tiempo, el espectro radioeléctrico, si bien está formalmente asignado a algún servicio, no se utiliza plenamente existiendo tiempos durante los cuales ciertas bandas están libres y potencialmente podrían ser usadas. Esto ha llevado a que las Redes Radios Cognitivas, concepto que existe desde hace un tiempo, sean consideradas uno de los pilares para el desarrollo de las redes inalámbricas del futuro. En los ultimos años la transferencia inalámbrica de energía (WPT) ha cobrado especial atención, ya que logra aumentar la robustez, usabilidad y autonomía de los dispositivos móviles. Transferir energía inalámbricamente relaja el compromiso entre el tamaño de la batería y la disponibilidad de energía, permitiendo aplicaciones que de otro modo no serían posibles. Esta tesis tiene como objetivo desarrollar técnicas novedosas para aumentar la eficiencia y la distancia de transmisión de sistemas de transferencia inalámbrica por acople inductivo (IPT). Se abordó el diseño del enlace inductivo y varios circuitos utilizados en el receptor de energía. Además, realizamos un cuidadoso análisis a nivel sistema, teniendo en cuenta el diseño conjunto de diferentes bloques. Todo el trabajo está orientado hacia el desarrollo de aplicaciones de bajo consumo, como dispositivos médicos implantables activos (AIMD) o sistemas de identificación por radio frecuencia (RFID). Se consideraron principalmente tres enfoques para lograr mayor eficienciay distancia: 1) El uso de bobinas resonantes adicionales, colocadas entre el transmisor y el receptor. 2) El uso de redes de adaptación de impedancia en el receptor. 3) El diseño de circuitos rectificdores y conversores dc-dc con alta eficiencia.El efecto ocasionado por las bobinas resonantes adicionales en el enlace inductivo es usualmente abordado sin tener en cuenta su influenciaen todas las partes del sistema. En este trabajo, analizamos teóricamente y comparamos sistemas de 2 y 3 bobinas, mostrando las ventajas que tiene la bobina adicional en conjunto con el uso de redes de adaptación. El efecto de dicha bobina, en sistemas de lazo cerrado fue también estudiado, demostrando que el diseño del lazo debe considerar el número de bobinas que utiliza el link. Se trabajó con un sistema real de RFID, analizando el uso de una bobina resonante en una aplicación práctica existente y de amplio uso en el Uruguay

Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes

Bidirectional neural interfaces are tools designed to “communicate” with the brain via recording and modulation of neuronal activity. The bidirectional interface systems have been adopted for many applications. Neuroscientists employ them to map neuronal circuits through precise stimulation and recording. Medical doctors deploy them as adaptable medical devices which control therapeutic stimulation parameters based on monitoring real-time neural activity. Brain-machine-interface (BMI) researchers use neural interfaces to bypass the nervous system and directly control neuroprosthetics or brain-computer-interface (BCI) spellers. In bidirectional interfaces, the implantable transducers as well as the corresponding electronic circuits and systems face several challenges. A high channel count, low power consumption, and reduced system size are desirable for potential chronic deployment and wider applicability. Moreover, a neural interface designed for robust closed-loop operation requires the mitigation of stimulation artifacts which corrupt the recorded signals. This dissertation introduces several techniques targeting low power consumption, small size, and reduction of stimulation artifacts. These techniques are implemented for extracellular electrophysiological recording and two stimulation modalities: direct current stimulation for closed-loop control of seizure detection/quench and optical stimulation for optogenetic studies. While the two modalities differ in their mechanisms, hardware implementation, and applications, they share many crucial system-level challenges. The first method aims at solving the critical issue of stimulation artifacts saturating the preamplifier in the recording front-end. To prevent saturation, a novel mixed-signal stimulation artifact cancellation circuit is devised to subtract the artifact before amplification and maintain the standard input range of a power-hungry preamplifier. Additional novel techniques have been also implemented to lower the noise and power consumption. A common average referencing (CAR) front-end circuit eliminates the cross-channel common mode noise by averaging and subtracting it in analog domain. A range-adapting SAR ADC saves additional power by eliminating unnecessary conversion cycles when the input signal is small. Measurements of an integrated circuit (IC) prototype demonstrate the attenuation of stimulation artifacts by up to 42 dB and cross-channel noise suppression by up to 39.8 dB. The power consumption per channel is maintained at 330 nW, while the area per channel is only 0.17 mm2. The second system implements a compact headstage for closed-loop optogenetic stimulation and electrophysiological recording. This design targets a miniaturized form factor, high channel count, and high-precision stimulation control suitable for rodent in-vivo optogenetic studies. Monolithically integrated optoelectrodes (which include 12 µLEDs for optical stimulation and 12 electrical recording sites) are combined with an off-the-shelf recording IC and a custom-designed high-precision LED driver. 32 recording and 12 stimulation channels can be individually accessed and controlled on a small headstage with dimensions of 2.16 x 2.38 x 0.35 cm and mass of 1.9 g. A third system prototype improves the optogenetic headstage prototype by furthering system integration and improving power efficiency facilitating wireless operation. The custom application-specific integrated circuit (ASIC) combines recording and stimulation channels with a power management unit, allowing the system to be powered by an ultra-light Li-ion battery. Additionally, the µLED drivers include a high-resolution arbitrary waveform generation mode for shaping of µLED current pulses to preemptively reduce artifacts. A prototype IC occupies 7.66 mm2, consumes 3.04 mW under typical operating conditions, and the optical pulse shaping scheme can attenuate stimulation artifacts by up to 3x with a Gaussian-rise pulse rise time under 1 ms.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147674/1/mendrela_1.pd

Development and modelling of a versatile active micro-electrode array for high density in-vivo and in-vitro neural signal investigation

The electrophysiological observation of neurological cells has allowed much knowledge to be gathered regarding how living organisms are believed to acquire and process sensation. Although much has been learned about neurons in isolation, there is much more to be discovered in how these neurons communicate within large networks. The challenges of measuring neurological networks at the scale, density and chronic level of non invasiveness required to observe neurological processing and decision making are manifold, however methods have been suggested that have allowed small scale networks to be observed using arrays of micro-fabricated electrodes. These arrays transduce ionic perturbations local to the cell membrane in the extracellular fluid into small electrical signals within the metal that may be measured. A device was designed for optimal electrical matching to the electrode interface and maximal signal preservation of the received extracellular neural signals. Design parameters were developed from electrophysiological computer simulations and experimentally obtained empirical models of the electrode-electrolyte interface. From this information, a novel interface based signal filtering method was developed that enabled high density amplifier interface circuitry to be realised. A novel prototype monolithic active electrode was developed using CMOS microfabrication technology. The device uses the top metallization of a selected process to form the electrode substrate and compact amplification circuitry fabricated directly beneath the electrode to amplify and separate the neural signal from the baseline offsets and noise of the electrode interface. The signal is then buffered for high speed sampling and switched signal routing. Prototype 16 and 256 active electrode array with custom support circuitry is presented at the layout stage for a 20 μm diameter 100 μm pitch electrode array. Each device consumes 26.4 μW of power and contributes 4.509 μV (rms) of noise to the received signal over a controlled bandwidth of 10 Hz - 5 kHz. The research has provided a fundamental insight into the challenges of high density neural network observation, both in the passive and the active manner. The thesis concludes that power consumption is the fundamental limiting factor of high density integrated MEA circuitry; low power dissipation being crucial for the existence of the surface adhered cells under measurement. With transistor sizing, noise and signal slewing each being inversely proportional to the dc supply current and the large power requirements of desirable ancillary circuitry such as analogue-to-digital converters, a situation of compromise is approached that must be carefully considered for specific application design

Circuit Design and Routing For Field Programmable Analog Arrays

Accurate, low-cost, rapid-prototyping techniques for analog circuits have been a long awaited dream for analog designers. However, due to the inherent nature of analog system, design automation in analog domain is very difficult to realize, and field programmable analog arrays (FPAA) have not achieved the same success as FPGAs in the digital domain. This results from several factors, including the lack of supporting CAD tools, small circuit density, low speed and significant parasitic effect from the fixed routing wires. These factors are all related to each other, making the design of a high performance FPAA a multi-dimension problem. Among others, a critical reason behind these difficulties is the non-ideal programming technology, which contributes a large portion of parasitics into the sensitive analog system, thus degrades the system performance. This work is trying to attack these difficulties with development of a laser field programmable analog array (LFPAA). There are two parts of work involved, routing for FPAA and analog IC building block design. To facilitate the router development and provide a platform for FPAA application development, a generic arrayed based FPAA architecture and a flexible CAB topology were proposed. The routing algorithm was based on a modified and improved pathfinder negotiated routing algorithm, and was implemented in C for a prototype FPAA. The parasitic constraints for performance analog routing were also investigated and solutions were proposed. In the area of analog circuit design, a novel differential difference op amp was invented as the core building block. Two bandgap circuits including a low voltage version were developed to generate a stable reference voltage for the FPAA. Based on the proposed FPAA architecture, several application examples were demonstrated. The results show the flexible functionality of the FPAA. Moreover, various laser Makelink test structures were studied on different CMOS processes and BiCMOS copper process. Laser Makelink proves to be a powerful programming technology for analog IC design. A novel laser Makelink trimming method was invented to reduce the op amp offset. The application of using laser Makelink to reconfigure the analog circuit blocks was presented