A 300-800MHz Tunable Filter and Linearized LNA applied in a Low-Noise Harmonic-Rejection RF-Sampling Receiver

A multiband flexible RF-sampling receiver aimed at software-defined radio is presented. The wideband RF sampling function is enabled by a recently proposed discrete-time mixing downconverter. This work exploits a voltage-sensing LNA preceded by a tunable LC pre-filter with one external coil to demonstrate an RF-sampling receiver with low noise figure (NF) and high harmonic rejection (HR). The second-order LC filter provides voltage pre-gain and attenuates the source noise aliasing, and it also improves the HR ratio of the sampling downconverter. The LNA consists of a simple amplifier topology built from inverters and resistors to improve the third-order nonlinearity via an enhanced voltage mirror technique. The RF-sampling receiver employs 8 times oversampling covering 300 to 800 MHz in two RF sub-bands. The chip is realized in 65 nm CMOS and the measured gain across the band is between 22 and 28 dB, while achieving a NF between 0.8 to 4.3 dB. The IIP2 varies between +38 and +49 dBm and the IIP3 between -14 dBm and -9 dBm, and the third and fifth order HR ratios are more than 60 dB. The LNA and downconverter consumes 6 mW, and the clock generator takes 12 mW at 800 MHz RF.\ud \u

High Performance LNAs and Mixers for Direct Conversion Receivers in BiCMOS and CMOS Technologies

The trend in cellular chipset design today is to incorporate support for a larger number of frequency bands for each new chipset generation. If the chipset also supports receiver diversity two low noise amplifiers (LNAs) are required for each frequency band. This is however associated with an increase of off-chip components, i.e. matching components for the LNA inputs, as well as complex routing of the RF input signals. If balanced LNAs are implemented the routing complexity is further increased. The first presented work in this thesis is a novel multiband low noise single ended LNA and mixer architecture. The mixer has a novel feedback loop suppressing both second order distortion as well as DC-offset. The performance, verified by Monte Carlo simulations, is sufficient for a WCDMA application. The second presented work is a single ended multiband LNA with programmable integrated matching. The LNA is connected to an on-chip tunable balun generating differential RF signals for a differential mixer. The combination of the narrow band input matching and narrow band balun of the presented LNA is beneficial for suppressing third harmonic downconversion of a WLAN interferer. The single ended architecture has great advantages regarding PCB routing of the RF input signals but is on the other hand more sensitive to common mode interferers, e.g. ground, supply and substrate noise. An analysis of direct conversion receiver requirements is presented together with an overview of different LNA and mixer architectures in both BiCMOS and CMOS technology

Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios

Next-generation wireless communication systems put more stringent performance requirements on the wireless RF receiver circuits. Sensitivity, linearity, bandwidth and power consumption are some of the most important specifications that often face tightly coupled tradeoffs between them. To increase the data throughput, a large number of fragmented spectrums are being introduced to the wireless communication standards. Carrier aggregation technology needs concurrent communication across several non-contiguous frequency bands, which results in a rapidly growing number of band combinations. Supporting all the frequency bands and their aggregation combinations increases the complexity of the RF receivers. Highly flexible software defined radio (SDR) is a promising technology to address these applications scenarios with lower complexity by relaxing the specifications of the RF filters or eliminating them. However, there are still many technology challenges with both the receiver architecture and the circuit implementations. The performance requirements of the receivers can also vary across different application scenario and RF environments. Field-programmable dynamic performance tradeoff can potentially reduce the power consumption of the receiver. In this dissertation, we address the performance enhancement challenges in the wideband SDRs by innovations at both the circuit building block level and the receiver architecture level. A series of research projects are conducted to push the state-of-the-art performance envelope and add features such as field-programmable performance tradeoff and concurrent reception. The projects originate from the concept of thermal noise canceling techniques and further enhance the RF performance and add features for more capable SDR receivers. Four generations of prototype LNA or receiver chips are designed, and each of them pushes at least one aspect of the RF performance such as bandwidth, linearity, and NF. A noise-canceling distributed LNA breaks the tradeoff between NF and RF bandwidth by introducing microwave circuit techniques from the distributed amplifiers. The LNA architecture uniquely provides ultra high bandwidth and low NF at low frequencies. A family of field-programmable LNA realized field-programmable performance tradeoff with current-reuse programmable transconductance cells. Interferer-reflecting loops can be applied around the LNAs to improve their input linearity by rejecting the out-of-band interferers with a wideband low in- put impedance. A low noise transconductance amplifier (LNTA) that operates in class-AB-C is invented to can handle rail-to-rail out-of-band blocker without saturation. Class-AB and class-C transconductors form a composite amplifier to increase the linear range of the input voltage. A new antenna interface named frequency-translational quadrature-hybrid (FTQH) breaks the input impedance matching requirement of the LNAs by introducing quadrature hybrid couplers to the CMOS RFIC design. The FTQH receiver achieves wideband sub-1dB NF and supports scalable massive frequency-agile concurrent reception

High Linearity Broadband RF Vector Multiplier for Analog/RF Pre-distortion

Wireless communication systems are moving towards a heterogeneous solution, where small-cell base stations such as pico-cells and femto-cells are used concurrently with macro- cell base stations in high data traffic areas. Small-cell networks are expected to provide much larger wireless data rates and capacity in small areas while only consuming a fraction of the power. However, power amplifier nonlinearity does not scale down with the size of the base station; a similar degree of nonlinearity correction is required in both small-cell and macro-cell base stations, meaning that the power consumed by the signal linearization circuits is the same. An analog-radio frequency pre-distortion (ARF-PD) solution, operating at a fraction of a conventional digital pre-distortion's power consumption, has been proposed to support the unrestrained growth of wireless communication. This thesis forms part of an ongoing research project aimed at developing a fully integrated ARF-PD solution - a promising, low-power alternative to digital pre-distortion for future wireless communications. Specifically, it focuses on delivering an integrated design of a low-power high-linearity broadband radio frequency (RF) vector multiplier, which can be used as part of the ARF-PD solution. An RF vector multiplier is considered one of the major function blocks in analog pre-distortion solutions, as it allows the analog pre-distorter to interface with the undistorted signal in the RF domain. In the thesis, two RF vector multiplier designs are proposed and implemented in integrated circuits. In the first implementation, the RF vector multiplier is designed to directly apply pre-distortion to the RF signal. This architecture imposes a need for high gain in the RF vector multiplier, which results in large transistor size and high power consumption in the output stage. The design is able to achieve promising simulation results, however, performance limitations and disadvantages are also clearly exposed compared to commercial products. To resolve the issues discovered, an alternative ARF-PD architecture is adopted to relax the output power level needed from the RF vector multiplier. In addition, a self-linearized variable gain amplifier topology is proposed to improve system linearity. Overall, the second design shows significant improvement in bandwidth, linearity and output noise level, while only consuming half of the power consumed by the first design. Ultimately, simulation results have shown satisfying performance for both RF vector multipliers as part of an ARF-PD system. However, both of the proposed integrated circuit designs should be validated by measurement

Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

Integration of broadband direct-conversion quadrature modulators

To increase spectral efficiency, transmitters usually send only one of the information carrying sidebands centered around a single radio-frequency carrier. The close-lying mirror, or image, sideband will be eliminated either by the filtering method or by the phasing method. Since filter Q-values rise in direct relation to the transmitted frequencies, the filtering method is generally not feasible for integrated microwave transmitters. A quadrature modulator realizes the phasing method by combining signals phased at quadrature (i.e. at 90° offsets) to produce a single-sideband (SSB) output. In this way output filtering can be removed or its specifications greatly relieved so as to produce an economical microwave transmitter. The proliferation of integrated circuit (IC) technologies since the 1980s has further boosted the popularity of quadrature modulator as an IC realization makes possible the economical production of two closely matched doubly balanced mixers, which suppress carrier and even-order spurious leakage to circuit output. Another strength of IC is its ability to perform microwave quadrature generation accurately on-chip, and thereby to avoid most of the interconnect parasitics which could ruin high-frequency quadrature signaling. Nevertheless, all quadrature modulator implementations are sensitive to phasing and amplitude errors, which are born as a result of mismatches, from the use of inaccurate differential signaling, and from inadequacies in the phasing circuitry itself. A 2° phase error is easily produced, and it reduces the image-rejection ratio (IRR) to −30 dBc. Therefore, as baseband signals synthesized by digital signal processing (DSP) are sufficiently accurate, this thesis concentrates on analyzing and producing the microwave signal path of a direct-conversion quadrature modulator with special emphasis on broadband, multimode radio-compatible operation. A model of the direct-conversion quadrature modulator operation has been developed, which reveals the effect the circuit non-linearities and mismatch-related offsets have on available performance. Further, theoretical proof is given of the well-known property of improving differential signal balance that cascaded differential pairs exhibit. Among the practical results, a current reuse mixer has been developed, which improves the transmitted signal-to-noise-ratio (SNR) by 3 dB, with a maximum measured dynamic range of +158 dB. The complementary bipolar process was further used to extend the bipolar push-pull stage bandwidth to 9.5 GHz. At the core of this work is the parallel switchable polyphase (PP) filter quadrature generator that was developed, since it makes possible accurate broadband IQ generation without the high loss that usually results from the application of PP filtering. Two IQ modulator prototypes were realized to test simulated and theoretically derived data: the 0.8 µm SiGe IC achieves an IRR better than −40 dBc over 0.75-3.6 GHz, while the 0.13 µm digital bulk CMOS IC achieves better than −37 dBc over 0.56-4.76 GHz. For this IRR performance the SiGe prototype boasts the inexpensive solution of integrated baluns, while the CMOS one utilizes a coil-transmission line hybrid transformer at its LO input to drive the switchable PP filters.Taajuuksien käytön tehostamiseksi lähettimet lähettävät yleensä vain toisen informaatiota sisältävistä sivukaistoistaan yhdelle radiotaajuuksiselle kantoaallolle keskitettynä. Viereinen peilitaajuus eli sivukaista vaimennetaan joko suodattamalla tai vaiheistamalla signalointia sopivasti. Koska suodattimen hyvyysluvut nousevat suorassa suhteessa käytettyyn taajuuteen, ei suodatusmenetelmä ole yleensä mahdollinen mikroaaltotaajuusalueen lähettimissä. Kvadratuurimodulaattori toteuttaa vaiheistusmenetelmän yhdistämällä 90-asteen vaihesiirroksin vaiheistetut signaalit yksisivukaistaisen lähetteen tuottamiseksi. Näin voidaan korvata lähdön suodatus joko kokonaan tai lieventämällä vaadittavia suoritusarvoja, jolloin mikroaaltoalueen lähetin voidaan tuottaa taloudellisesti. Integroitujen piiriratkaisujen yleistyminen 1980-luvulta lähtien on edesauttanut kvadratuurimodulaattorin suosiota, koska integroidulle piirille voidaan taloudellisesti tuottaa kaksi hyvin ominaisuuksiltaan toisiaan vastaavaa kaksoisbalansoitua sekoitinta, ja nämä tunnetusti vaimentavat kantoaaltovuotoa ja parillisia harmoonisia piirin lähdössä. Toinen integroitujen piirien vahvuus on kyky tarkkaan mikroaaltoalueen kvadratuurisignalointiin samalla piirillä, jolloin vältetään suurin osa kytkentöjen parasiittisista jotka muutoin voisivat tuhota korkeataajuuksisen 90-asteen vaiheistuksen. Kaikki kvadratuurimodulaattorit ovat joka tapauksessa herkkiä vaiheistus- ja amplitudieroille, joita syntyy komponenttiarvojen satunnaishajonnasta, epätarkan differentiaalisen signaloinnin käytöstä, ja itse vaiheistuspiiristön puutteellisuuksista. Kahden asteen vaihevirhe syntyy helposti, ja tällöin sivukaistavaimennus heikkenee -30 dBc:n tasolle. Tämänvuoksi, ja olettaen että digitaalisella signaaliprosessorilla luotu kantataajuuksinen signalointi on riittävän tarkkaa, tämä väitöskirja keskittyy kvadratuurimodulaattorin mikroaaltotaajuuksisen signaalipolun analysointiin ja tuottamiseen painottaen erityisesti laajakaistaista, monisovellusradioiden kanssa yhteensopivaa toimivuutta. Kvadratuurimodulaattorin toimintamallia on kehitetty siten, että mallissa huomioidaan epälineaarisuuksien ja piirielementtien satunnaishajontojen vaikutus saavutettavalle suorituskyvylle. Lisäksi on teoreettisesti todistettu sinänsä hyvin tunnettu peräkkäin kytkettyjen vahvistinasteiden differentiaalisen signaloinnin symmetrisyyttä parantava vaikutus. Käytännön tuloksista voidaan mainita kehitetty virtaakierrättävä sekoitin, joka parantaa signaali-kohinasuhdetta +3 dB, suurimman mitatun dynaamisen alueen ollessa +158 dB. Samaa komplementaarista bipolaariprosessia käytettiin edelleen bipolaarisen vuorovaihe-asteen kaistan levittämisessä 9.5 GHz:iin. Yhtenä tämän työn tärkeimmistä tuloksista on kehitetty kytkimin valittavista rinnakkaisista monivaihesuodattimista koostuva kvadratuurigeneraattori, jolla on mahdollista tuottaa laajakaistaista IQ-signalointia ilman suurta häviötä joka yleensä liittyy monivaihesuodattimien käyttöön. Kaksi IQ-modulaattoriprototyyppiä toteutettiin simuloitujen ja teoreettisesti mallinnettujen tulosten testaamiseksi: 0.8 µm SiGe integroitu piiri saavuttaa paremman sivukaistavaimennuksen kuin -40 dBc yli 0.75-3.6 GHz, kun taas 0.13 µm digitaalipiirien tuottamiseen tarkoitetulla CMOS prosessilla toteutettu integroitu piiri saavuttaa paremman sivukaistavaimennuksen kuin -37 dBc taajuusalueella 0.56-4.76 GHz. Näihin sivukaistavaimennuksiin SiGe prototyyppi pääsee edullisesti integroiduin symmetrointimuuntajin, kun taas CMOS piirillä käytetään kela-siirtojohto-tyyppistä yhdistelmämuuntajaa LO-sisääntulossa josta ajetaan erikseen kytkettäviä monivaihesuodattimia.reviewe

CMOS RF front-end design for terrestrial and mobile digital television systems

With the increasing demand for high quality TV service, digital television (DTV) is replacing the conventional analog television. DTV tuner is one of the most critical blocks of the DTV receiver system; it down-converts the desired DTV RF channel to baseband or a low intermediate frequency with enough quality. This research is mainly focused on the analysis and realization of low-cost low-power front-ends for ATSC terrestrial DTV and DVB-H mobile DTV tuner systems. For the design of the ATSC terrestrial tuner, a novel double quadrature tuner architecture, which can not only minimize the tuner power consumption but also achieve the fully integration, has been proposed. A double quadrature down-converter has been designed and fabricated with TSMC 0.35õm CMOS technology; the measurement results verified the proposed concepts. For the mobile DTV tuner, a zero-IF architecture is used and it can achieve the DVB-H specifications with less than 200mW power consumption. In the implementation of the mobile DVB-H tuner, a novel RF variable gain amplifier (RFVGA) and a low flicker noise current-mode passive mixer have been proposed. The proposed RFVGA achieves high dynamic range and robust input impedance matching performance, which is the main design challenge for the traditional implementations. The current-mode passive mixer achieves high-gain, low noise (especially low flicker noise) and high-linearity (over 10dBm IIP3) with low power supplies; it is believed that this is a promising topology for low voltage high dynamic range mixer applications. The RFVGA has been fabricated in TSMC 0.18õm CMOS technology and the measurement results agree well with the theoretical ones

Design of broadband inductor-less RF front-ends with high dynamic range for G.hn

System-on-Chip (SoC) was adopted in recent years as one of the solutions to reduce the cost of integrated systems. When the SoC solution started to be used, the final product was actually more expensive due to lower yield. The developments in integrated technology through the years allowed the integration of more components in lesser area with a better yield. Thus, SoCs became a widely used solution to reduced the cost of the final product, integrating into a single-chip the main parts of a system: analog, digital and memory. As integrated technology kept scaling down to allow a higher density of transistors and thus providing more functionality with the same die area, the analog RF parts of the SoC became a bottleneck to cost reduction as inductors occupy a large die area and do not scale down with technology. Hence, the trend moves toward the research and design of inductor-less SoCs that further reduce the cost of the final solution. Also, as the demand for home networking high-data-rates communication systems has increased over the last decade, several standards have been developed to satisfy the requirements of each application, the most popular being wireless local area networks (WLANs) based on the IEEE 802.11 standard. However, poor signal propagation across walls make WLANs unsuitable for high-speed applications such as high-definition in-home video streaming, leading to the development of wired technologies using the existing in-home infrastructure. The ITU-T G.hn recommendation (G.9960 and G.9961) unifies the most widely used wired infrastructures at home (coaxial cables, phone lines and power lines) into a single standard for high-speed data transmission of up to 1 Gb/s. The G.hn recommendation defines a unified networking over power lines, phone lines and coaxial cables with different plans for baseband and RF. The RF-coax bandplan, where this thesis is focused, uses 50 MHz and 100 MHz bandwidth channels with 256 and 512 carriers respectively. The center frequency can range from 350 MHz to 2450 MHz. The recommendation specifies a transmission power limit of 5 dBm for the 50 MHz bandplan and 8~dBm for the 100 MHz bandplan, therefore the maximum transmitted power in each carrier is the same for both bandplans. Due to the nature of an in-home wired environment, receivers that can handle both very large and very small amplitude signals are required; when transmitter and receiver are connected on the same electric outlet there is no channel attenuation and the signal-to-noise-plus-distortion ratio (SNDR) is dominated by the receiver linearity, whereas when transmitter and receiver are several rooms apart channel attenuation is high and the SNDR is dominated by the receiver noise figure. The high dynamic range specifications for these receivers require the use of configurable-gain topologies that can provide both high-linearity and low-noise for different configurations. Thus, this thesis has been aimed at researching high dynamic range broadband inductor-less topologies to be used as the RF front-end for a G.hn receiver complying with the provided specifications. A large part of the thesis has been focused on the design of the input amplifier of the front-end, which is the most critical stage as the noise figure and linearity of the input amplifier define the achievable overall specifications of the whole front-end. Three prototypes has been manufactured using a 65 nm CMOS process: two input RFPGAs and one front-end using the second RFPGA prototype.El "sistema en un chip" (SoC) fue adoptado recientemente como una de las soluciones para reducir el coste de sistemas integrados. Cuando se empezó a utilizar la solución SoC, el producto final era más caro debido al bajo rendimiento de producción. Los avances en tecnología integrada a lo largo de los años han permitido la integración de más componentes en menos área con mejoras en rendimiento. Por lo tanto, SoCs pasó a ser una solución ampliamente utilizada para reducir el coste del producto final, integrando en un único chip las principales partes de un sistema: analógica, digital y memoria. A medida que las tecnologías integradas se reducían en tamaño para permitir una mayor densisdad de transistores y proveer mayor funcionalidad con la misma área, las partes RF analógicas del SoC pasaron a ser la limitación en la reducción de costes ya que los inductores ocupan mucha área y no escalan con la tecnología. Por lo tanto, las tendencias en investigación se mueven hacia el diseño de SoCs sin inductores que todavía reducen más el coste final del producto. También, a medida que la demanda en sistemas de comunicación domésticos de alta velocidad ha crecido a lo largo de la última década, se han desarrollado varios estándares para satisfacer los requisitos de cada aplicación, siendo las redes sin hilos (WLANs) basadas en el estándar IEEE 802.11 las más populares. Sin embargo, una pobre propagación de señal a través de las paredes hacen que las WLANs sean inadecuadas para aplicaciones de alta-velocidad como transmisión de vídeo de alta definición en tiempo real, resultando en el desarrollo de tecnologías con hilos utilizando la infraestructura existente en los domicilios. La recomendación ITU-T G.hn (G.9960 and G.9961) unifica las principales infraestructuras con hilos domésticas (cables coaxiales, línias de teléfono y línias de electricidad) en un sólo estándar para la transmisión de datos hasta 1 Gb/s. La recomendación G.hn define una red unificada sobre línias de electricidad, de teléfono y coaxiales con diferentes esquemas para banda base y RF. El esquema RF-coax en el cual se basa esta tesis, usa canales con un ancho de banda de 50 MHz y 100 MHz con 256 y 512 portadoras respectivamente. La frecuencia centra puede variar desde 350 MHz hasta 2450 MHz. La recomendación especifica un límite en la potencia de transmisión de 5 dBm para el esquema de 50 MHz y 8 dBm para el esquema de 100 MHz, de tal forma que la potencia máxima por portadora es la misma en ambos esquemas. Debido a la estructura de un entorno doméstico con hilos, los receptores deben ser capaces de procesar señales con amplitud muy grande o muy pequeña; cuando transmisor y receptor están conectados en la misma toma eléctrica no hay atenuación de canal y el ratio de señal a rudio más distorsión (SNDR) está dominado por la linealidad del receptor, mientras que cuando transmisor y receptor están separados por varias habitaciones la atenuación es elevada y el SNDR está dominado por la figura de ruido del receptor. Los elevados requisitos de rango dinámico para este tipo de receptores requieren el uso de topologías de ganancia configurable que pueden proporcionar tanto alta linealidad como bajo ruido para diferentes configuraciones. Por lo tanto, esta tesis está encarada a la investigación de topologías sin inductores de banda ancha y elevado rango dinámico para ser usadas a la entrada de un receptor G.hn cumpliendo con las especificaciones proporcionadas. Una gran parte de la tesis se ha centrado en el diseño del amplificador de entrada al ser la etapa más crítica, ya que la figura de ruido y linealidad del amplificador de entrada definen lás máximas especificaciones que el sistema puede conseguir. Se han fabricado 3 prototipos con un proceso CMOS de 65 nm: 2 amplificadores y un sistema completo con amplificador y mezclador.Postprint (published version