A 1.2 V and 69 mW 60 GHz Multi-channel Tunable CMOS Receiver Design

A multi-channel receiver operating between 56 GHz and 70 GHz for coverage of different 60 GHz bands worldwide is implemented with a 90 nm Complementary Metal-Oxide Semiconductor (CMOS) process. The receiver containing an LNA, a frequency down-conversion mixer and a variable gain amplifier incorporating a band-pass filter is designed and implemented. This integrated receiver is tested at four channels of centre frequencies 58.3 GHz, 60.5 GHz, 62.6 GHz and 64.8 GHz, employing a frequency plan of an 8 GHz-intermediate frequency (IF). The achieved conversion gain by coarse gain control is between 4.8 dB–54.9 dB. The millimeter-wave receiver circuit is biased with a 1.2V supply voltage. The measured power consumption is 69 mW

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

Broadband RF Front-End Design for Multi-Standard Receiver with High-Linearity and Low-Noise Techniques

Future wireless communication devices must support multiple standards and features on a single-chip. The trend towards software-defined radio requires flexible and efficient RF building blocks which justifies the adoption of broadband receiver front-ends in modern and future communication systems. The broadband receiver front-end significantly reduces cost, area, pins, and power, and can process several signal channels simultaneously. This research is mainly focused on the analysis and realization of the broadband receiver architecture and its various building blocks (LNA, Active Balun-LNA, Mixer, and trans-impedance amplifier) for multi-standard applications. In the design of the mobile DTV tuner, a direct-conversion receiver architecture is adopted achieving low power, low cost, and high dynamic-range for DVB-H standard. The tuner integrates a single-ended RF variable gain amplifier (RFVGA), a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. The proposed RFVGA achieves high dynamic-range and gain-insensitive input impedance matching performance. The current-mode passive mixer achieves high gain, low noise, and high linearity with low power supplies. A wideband common-gate LNA is presented that overcomes the fundamental trade-off between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure over the previously reported feedback amplifiers in common-gate configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback. For the wideband Inductorless Balun-LNA, active single-to-differential architecture has been proposed without using any passive inductor on-chip which occupies a lot of silicon area. The proposed Balun-LNA features lower power, wider bandwidth, and better gain and phase balance than previously reported architectures of the same kind. A surface acoustic wave (SAW)-less direct conversion receiver targeted for multistandard applications is proposed and fabricated with TSMC 0.13?m complementary metal-oxide-semiconductor (CMOS) technology. The target is to design a wideband SAW-less direct coversion receiver with a single low noise transconductor and current-mode passive mixer with trans-impedance amplifier utilizing feed-forward compensation. The innovations in the circuit and architecture improves the receiver dynamic range enabling highly linear direct-conversion CMOS front-end for a multi-standard receiver

Design Considerations of a Sub-50 {\mu}W Receiver Front-end for Implantable Devices in MedRadio Band

Emerging health-monitor applications, such as information transmission through multi-channel neural implants, image and video communication from inside the body etc., calls for ultra-low active power (<50${\mu}$W) high data-rate, energy-scalable, highly energy-efficient (pJ/bit) radios. Previous literature has strongly focused on low average power duty-cycled radios or low power but low-date radios. In this paper, we investigate power performance trade-off of each front-end component in a conventional radio including active matching, down-conversion and RF/IF amplification and prioritize them based on highest performance/energy metric. The analysis reveals 50${\Omega}$ active matching and RF gain is prohibitive for 50${\mu}$W power-budget. A mixer-first architecture with an N-path mixer and a self-biased inverter based baseband LNA, designed in TSMC 65nm technology show that sub 50${\mu}$W performance can be achieved up to 10Mbps (< 5pJ/b) with OOK modulation.Comment: Accepted to appear on International Conference on VLSI Design 2018 (VLSID

Design issues and experimental characterization of a continuously-tuned adaptive CMOS LNA

This paper presents the design implementation and experimental characterization of an adaptive Low Noise Amplifier (LNA) intended for multi-standard Radio Frequency (RF) wireless transceivers. The circuit —fabricated in a 90-nm CMOS technology— is a two-stage inductively degenerated common-source topology that combines PMOS varactors with programmable load to make the operation of the circuit continuously tunable. Practical design issues are analyzed, considering the effect of circuit parasitics associated to the chip package and integrated inductors, capacitors and varactors. Experimental measurements show a continuous tuning of NF and Sparameters within the 1.75-2.23GHz band, featuring NF19.6dB and IIP3> −9.8dBm, with a power dissipation < 23mW from a 1-V supply voltage.Ministerio de Ciencia e Innovación (FEDER) TEC2007-67247-C02-01/MICJunta de Andalucía, Consejo Regional de Innovación, ciencia y empresa TIC-253

A Wideband Inductorless CMOS Front-End for Software Defined

The number of wireless communication links is witnessing tremendous growth and new standards are being introduced at high pace. These standards heavily rely on digital signal processing, making CMOS the first technology of choice. However, RF CMOS circuit development is costly and time consuming due to mask costs and design iterations. This pleads for a Software Defined Radio approach, in which one piece of flexible radio hardware is re-used for different applications and standards, downloadable and under software control. To the best of our knowledge, little work has been done in this field based on CMOS technology. Recently, a bipolar downconverter front-end has been proposed [1]. In CMOS, only wideband low-noise amplifiers have been proposed, and some CMOS tuner ICs for satellite reception (which have less stringent noise requirements because they are preceded by an outdoor low-noise converter). This paper presents a wideband RF downconverter frontend in 0.18 um CMOS (also published in [2]), designed in the context of a research project exploring the feasibility of software defined radio, using a combined Bluetooth/WLAN receiver as a vehicle. Usually, RF receivers are optimised for low power consumption. In contrast, we have taken the approach to optimise for flexibility. The paper discusses the main system and circuit design choices, and assesses the achievable performance via measurements on a front-end implemented in 0.18um CMOS. The flexible design achieves a 0.2-2.2 GHz -3 dB bandwidth, a gain of 25 dB with 6 dB noise figure and +1 dBm IIP3

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve