170 research outputs found
CMOS digital pixel sensor array with time domain analogue to digital conversion
This thesis presents a digital pixel sensor array, which is the first stage of an ongoing project to produce a CMOS image sensor with on-chip image processing. The analogue to digital conversion is performed at the pixel level, with the result stored in pixel memory. This architecture allows fast, reliable access to the image data and simplifies the integration of the image array and the processing logic. Each pixel contains a photodiode sensor, a comparator, memory and addressing logic. The photodiode sensor operates in integrating mode, where the photodiode junction capacitance is first charged to an initial voltage, and then discharged by the photodiode leakage current, which is comprised mainly of optically generated carriers. The analogue to digital conversion is performed by measuring the time taken for the photodiode cathode voltage to fall from its initial voltage, to the comparator reference voltage. This triggers the 8-bit pixel memory, which stores a data value representative of the time. The trigger signal also resets the photodiode, which conserves the charge stored in the junction capacitance, and also prevents blooming. An on-chip control circuit generates the digital data that is distributed globally to the array. The control circuit compensates for the inverse relationship between the integration time and the photocurrent by adjusting the data clock timing. The period of the data clock is increased at the same rate as the integration time, resulting in a linear relationship between the digital data and the photocurrent. The design is realised as a 64 x 64 pixel array, manufactured in O.35µm 3.3 V CMOS technology. Each pixel occupies an area of 45µm x 45µm with a 12.3% fill factor, and the entire pixel array and control circuit measures 3.7mm x 3.9mm. Experimental results confirm the operation of the digital pixel, and the linearising control circuit. The digital pixel has a dynamic range of 85dB, and can be adapted to different lighting conditions by varying a single clock frequency. The data captured by the array can be randomly accessed, and is read from the array nondestructivcly
Low-power CMOS digital-pixel Imagers for high-speed uncooled PbSe IR applications
This PhD dissertation describes the research and development of a new low-cost medium wavelength infrared MWIR monolithic imager technology
for high-speed uncooled industrial applications. It takes the baton on the latest technological advances in the field of vapour phase deposition (VPD)
PbSe-based medium wavelength IR (MWIR) detection accomplished by the industrial partner NIT S.L., adding fundamental knowledge on the investigation of novel VLSI analog and mixed-signal design techniques at circuit and system levels for the development of the readout integrated device attached to the detector.
The work supports on the hypothesis that, by the use of the preceding design techniques, current standard inexpensive CMOS technologies fulfill all
operational requirements of the VPD PbSe detector in terms of connectivity, reliability, functionality and scalability to integrate the device. The resulting monolithic PbSe-CMOS camera must consume very low power, operate at kHz frequencies, exhibit good uniformity and fit the CMOS read-out active pixels in the compact pitch of the focal plane, all while addressing the particular characteristics of the MWIR detector: high dark-to-signal ratios, large input parasitic capacitance values and remarkable mismatching in PbSe integration.
In order to achieve these demands, this thesis proposes null inter-pixel crosstalk vision sensor architectures based on a digital-only focal plane array (FPA) of configurable pixel sensors. Each digital pixel sensor (DPS) cell is equipped with fast communication modules, self-biasing, offset cancellation, analog-to-digital converter (ADC) and fixed pattern noise (FPN) correction. In-pixel power consumption is minimized by the use of comprehensive MOSFET subthreshold operation.
The main aim is to potentiate the integration of PbSe-based infra-red (IR)-image sensing technologies so as to widen its use, not only in distinct scenarios, but also at different stages of PbSe-CMOS integration maturity. For this purpose, we posit to investigate a comprehensive set of functional blocks distributed in two parallel approaches:
• Frame-based “Smart” MWIR imaging based on new DPS circuit topologies with gain and offset FPN correction capabilities. This research
line exploits the detector pitch to offer fully-digital programmability at pixel level and complete functionality with input parasitic capacitance compensation and internal frame memory.
• Frame-free “Compact”-pitch MWIR vision based on a novel DPS lossless analog integrator and configurable temporal difference, combined with asynchronous communication protocols inside the focal plane. This strategy is conceived to allow extensive pitch compaction and readout speed increase by the suppression of in-pixel digital filtering, and the use of dynamic bandwidth allocation in each pixel of the FPA.
In order make the electrical validation of first prototypes independent of the expensive PbSe deposition processes at wafer level, investigation is extended as well to the development of affordable sensor emulation strategies and integrated test platforms specifically oriented to image read-out integrated circuits. DPS cells, imagers and test chips have been fabricated and characterized in standard 0.15μm 1P6M, 0.35μm 2P4M and 2.5μm 2P1M CMOS technologies, all as part of research projects with industrial partnership.
The research has led to the first high-speed uncooled frame-based IR quantum imager monolithically fabricated in a standard VLSI CMOS technology, and has given rise to the Tachyon series [1], a new line of commercial IR cameras used in real-time industrial, environmental and transportation control systems. The frame-free architectures investigated in this work represent a firm step forward to push further pixel pitch and system bandwidth up to the limits imposed by the evolving PbSe detector in future generations of the device.La present tesi doctoral descriu la recerca i el desenvolupament d'una nova tecnologia monolítica d'imatgeria infraroja de longitud d'ona mitja (MWIR), no refrigerada i de baix cost, per a usos industrials d'alta velocitat. El treball pren el relleu dels últims avenços assolits pel soci industrial NIT S.L. en el camp dels detectors MWIR de PbSe depositats en fase vapor (VPD), afegint-hi coneixement fonamental en la investigació de noves tècniques de disseny de circuits VLSI analògics i mixtes pel desenvolupament del dispositiu integrat de lectura unit al detector pixelat. Es parteix de la hipòtesi que, mitjançant l'ús de les esmentades tècniques de disseny, les tecnologies CMOS estàndard satisfan tots els requeriments operacionals del detector VPD PbSe respecte a connectivitat, fiabilitat, funcionalitat i escalabilitat per integrar de forma econòmica el dispositiu. La càmera PbSe-CMOS resultant ha de consumir molt baixa potència, operar a freqüències de kHz, exhibir bona uniformitat, i encabir els píxels actius CMOS de lectura en el pitch compacte del pla focal de la imatge, tot atenent a les particulars característiques del detector: altes relacions de corrent d'obscuritat a senyal, elevats valors de capacitat paràsita a l'entrada i dispersions importants en el procés de fabricació. Amb la finalitat de complir amb els requisits previs, es proposen arquitectures de sensors de visió de molt baix acoblament interpíxel basades en l'ús d'una matriu de pla focal (FPA) de píxels actius exclusivament digitals. Cada píxel sensor digital (DPS) està equipat amb mòduls de comunicació d'alta velocitat, autopolarització, cancel·lació de l'offset, conversió analògica-digital (ADC) i correcció del soroll de patró fixe (FPN). El consum en cada cel·la es minimitza fent un ús exhaustiu del MOSFET operant en subllindar. L'objectiu últim és potenciar la integració de les tecnologies de sensat d'imatge infraroja (IR) basades en PbSe per expandir-ne el seu ús, no només a diferents escenaris, sinó també en diferents estadis de maduresa de la integració PbSe-CMOS. En aquest sentit, es proposa investigar un conjunt complet de blocs funcionals distribuïts en dos enfocs paral·lels: - Dispositius d'imatgeria MWIR "Smart" basats en frames utilitzant noves topologies de circuit DPS amb correcció de l'FPN en guany i offset. Aquesta línia de recerca exprimeix el pitch del detector per oferir una programabilitat completament digital a nivell de píxel i plena funcionalitat amb compensació de la capacitat paràsita d'entrada i memòria interna de fotograma. - Dispositius de visió MWIR "Compact"-pitch "frame-free" en base a un novedós esquema d'integració analògica en el DPS i diferenciació temporal configurable, combinats amb protocols de comunicació asíncrons dins del pla focal. Aquesta estratègia es concep per permetre una alta compactació del pitch i un increment de la velocitat de lectura, mitjançant la supressió del filtrat digital intern i l'assignació dinàmica de l'ample de banda a cada píxel de l'FPA. Per tal d'independitzar la validació elèctrica dels primers prototips respecte a costosos processos de deposició del PbSe sensor a nivell d'oblia, la recerca s'amplia també al desenvolupament de noves estratègies d'emulació del detector d'IR i plataformes de test integrades especialment orientades a circuits integrats de lectura d'imatge. Cel·les DPS, dispositius d'imatge i xips de test s'han fabricat i caracteritzat, respectivament, en tecnologies CMOS estàndard 0.15 micres 1P6M, 0.35 micres 2P4M i 2.5 micres 2P1M, tots dins el marc de projectes de recerca amb socis industrials. Aquest treball ha conduït a la fabricació del primer dispositiu quàntic d'imatgeria IR d'alta velocitat, no refrigerat, basat en frames, i monolíticament fabricat en tecnologia VLSI CMOS estàndard, i ha donat lloc a Tachyon, una nova línia de càmeres IR comercials emprades en sistemes de control industrial, mediambiental i de transport en temps real.Postprint (published version
Low-power CMOS circuit design for fast infrared imagers
La present tesi de màster detalla novedoses tècniques circuitals per al disseny de circuits integrats digitals CMOS de lectura compactes, de baixa potència i completament programables, destinats a aplicacions d'IR d'alta velocitat operant a temperatura ambient. En aquest sentit, el treball recull i amplia notablement la recerca iniciada en el Projecte Final de Carrera "Tècniques de disseny CMOS per a sistemes de visió híbrids de pla focal modular" obtenint-se resultats específics en tres diferents àrees: Recerca de l'arquitectura òptima d'FPA, des del punt de vista funcional i de construcció física. Disseny d'un conjunt complet de blocs bàsics d'autopolarització, compensació de la capacitat d'entrada i del corrent d'obscuritat, conversió A/D i interfície d'E/S exclusivament digital, amb compensació de l'FPN. Aplicació industrial real: Integraciió de tres versions diferents de píxel per sensors PbSe d'IR i fabricació de mòduls ROIC monolítics i híbrids en tecnologia CMOS estàndard 0.35&·956;m 2-PoliSi4-metall. Caracterització elèctrica i òptica-preliminar de les llibreries de disseny
A full-custom digital-signal-processing unit for real-time cortical blood flow monitoring
Master'sMASTER OF ENGINEERIN
A CMOS 90nm Digital Pixel Sensor Intended for a Visual Cortical Stimulator
RÉSUMÉ La capture d’images et le traitement d’images et de signaux font partie des domaines les plus en vogue de nos jours. Un autre domaine qui retient l’attention des chercheurs à travers le monde est celui qui regroupe les applications biomédicales - en particulier celles qui font le pont entre l’électronique et la biologie. L’équipe Polystim œuvre sur différents projets à la pointe de la technologie qui touchent à ces domaines, dont le projet Cortivision: un stimulateur visuel cortical. Le système englobe la capture et le traitement d’images ainsi que la stimulation du cortex pour donner une certaine perception d’images aux patients souffrant de cécité. Le but de ce travail est de concevoir le module de capture d’images de ce système. Les modes d’opération du capteur d’images doivent être configurables par l’usager. Il doit se distinguer par une gamme dynamique élevée, une consommation de puissance réduite, une haute vitesse d’acquisition, une surface réduite, la portabilité, la possibilité d’avoir du traitement d’images sur puce, et la facilité de l’intégrer dans un système sur puce avec le reste des modules de Cortivision. Un DPS (Digital Pixel Sensor) CMOS a été conçu et fabriqué avec la nouvelle technologie CMOS 90nm. Chaque pixel comprend une photodiode, un circuit de conversion de photocourant, un convertisseur analogique à numérique et une mémoire numérique de 8 bits, dans une surface de 9 µm x 9 µm avec un facteur de remplissage de 26% et 57 transistors. Le capteur offre plusieurs modes d’opération:
• Un mode d’intégration linéaire. • Un mode logarithmique avec une gamme dynamique étendue qui permet d’accéder aux pixels indépendamment du temps mais avec une diminution de linéarité et un bruit plus prononcé. • Un mode différentiel qui soustrait deux images successives à même la puce pour obtenir une image binaire. Ce mode permet d’accélérer le traitement d’images et fonctionne à une vitesse plus élevée. Il peut être utilisé simultanément avec le mode linéaire ou avec le mode logarithmique. • Un mode d’expositions multiples qui est une option du mode linéaire pour augmenter la gamme dynamique, mais qui aurait l’effet de réduire la vitesse d’acquisition.----------ABSTRACT The image sensing and image processing fields make up some of the hottest topics in today’s industrial and research communities. Another field that is getting a lot of attention is biomedical applications - especially the combination of electronics to biology. The Polystim team is working on some state-of-the-art projects encompassing all that. One of these is the Cortivision project that consists of a visual cortical stimulator. The system comprises image sensing, image processing, and brain cortex stimulation to help blind patients acquire a sense of visual perception.
The goal of this work is to cover the image sensing portion of the system. This requires the design and implementation of an image sensor which is user configurable to operate in several modes, has a high dynamic range, low power consumption, high frame rate capability, reduced surface area, is portable, allows some on-chip image processing, and can easily be integrated in a system-on-chip with the rest of the Cortivision modules.
A CMOS Digital Pixel Sensor was designed and fabricated using the novel CMOS 90nm technology. Each pixel consists of a Photodiode, a photo-current conversion circuit, an Analog-to-Digital Converter and a digital 8-bit memory. It has a pixel pitch of 9µm with a Fill-Factor of 26% and 57 transistors. The sensor offers several modes of operation:
• A linear integration mode.
• A logarithmic mode that extends the dynamic range and allows time-independent pixel access at the cost of a forsaken linearity and an increase in noise. • A differential (or better termed difference) mode that allows subtracting two consecutive frames to obtain a binary image. This mode helps speed up the image processing and allows a very high frame rate. It can be used in conjunction with either the linear or the logarithmic modes of operation. • A multiple exposure mode that can be used in combination with the linear mode to increase the dynamic range at the expense of a decrease in frame rate
Novel Front-end Electronics for Time Projection Chamber Detectors
Este trabajo ha sido realizado en la Organización Europea para la Investigación Nuclear (CERN) y forma parte del proyecto de investigación Europeo para futuros aceleradores lineales (EUDET).
En física de partículas existen diferentes categorías de detectores de partículas. El diseño presentado esta centrado en un tipo particular de detector de trayectoria de partículas denominado TPC (Time Projection Chamber) que proporciona una imagen en tres dimensiones de las partículas eléctricamente cargadas que atraviesan su volumen gaseoso.
La tesis incluye un estudio de los objetivos para futuros detectores, resumiendo los parámetros que un sistema de adquisición de datos debe cumplir en esos casos. Además, estos requisitos son comparados con los actuales sistemas de lectura utilizados en diferentes detectores TPC. Se concluye que ninguno de los sistemas cumple las restrictivas condiciones. Algunos de los principales objetivos para futuros detectores TPC son un altísimo nivel de integración, incremento del número de canales, electrónica más rápida y muy baja potencia.
El principal inconveniente del estado del arte de los sistemas anteriores es la utilización de varios circuitos integrados en la cadena de adquisición. Este hecho hace imposible alcanzar el altísimo nivel de integración requerido para futuros detectores. Además, un aumento del número de canales y frecuencia de muestreo haría incrementar hasta valores no permitidos la potencia utilizada. Y en consecuencia, incrementar la refrigeración necesaria (en caso de ser posible).
Una de las novedades presentadas es la integración de toda la cadena de adquisición (filtros analógicos de entrada, conversor analógico-digital (ADC) y procesado de señal digital) en un único circuito integrado en tecnología de 130nm. Este chip es el primero que realiza esta altísima integración para detectores TPC.
Por otro lado, se presenta un análisis detallado de los filtros de procesado de señal. Los objetivos más importantes es la reduccióGarcía García, EJ. (2012). Novel Front-end Electronics for Time Projection Chamber Detectors [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/16980Palanci
Propuesta de arquitectura y circuitos para la mejora del rango dinámico de sistemas de visión en un chip diseñados en tecnologías CMOS profundamente submicrométrica
El trabajo presentado en esta tesis trata de proponer nuevas técnicas para la expansión
del rango dinámico en sensores electrónicos de imagen. En este caso, hemos dirigido nuestros
estudios hacia la posibilidad de proveer dicha funcionalidad en un solo chip. Esto es, sin
necesitar ningún soporte externo de hardware o software, formando un tipo de sistema
denominado Sistema de Visión en un Chip (VSoC). El rango dinámico de los sensores
electrónicos de imagen se define como el cociente entre la máxima y la mínima iluminación
medible. Para mejorar este factor surgen dos opciones. La primera, reducir la mínima luz
medible mediante la disminución del ruido en el sensor de imagen. La segunda, incrementar la
máxima luz medible mediante la extensión del límite de saturación del sensor.
Cronológicamente, nuestra primera opción para mejorar el rango dinámico se basó en
reducir el ruido. Varias opciones se pueden tomar para mejorar la figura de mérito de ruido del
sistema: reducir el ruido usando una tecnología CIS o usar circuitos dedicados, tales como
calibración o auto cero. Sin embargo, el uso de técnicas de circuitos implica limitaciones, las
cuales sólo pueden ser resueltas mediante el uso de tecnologías no estándar que están
especialmente diseñadas para este propósito. La tecnología CIS utilizada está dirigida a la
mejora de la calidad y las posibilidades del proceso de fotosensado, tales como sensibilidad,
ruido, permitir imagen a color, etcétera. Para estudiar las características de la tecnología en más
detalle, se diseñó un chip de test, lo cual permite extraer las mejores opciones para futuros
píxeles. No obstante, a pesar de un satisfactorio comportamiento general, las medidas referentes
al rango dinámico indicaron que la mejora de este mediante sólo tecnología CIS es muy
limitada. Es decir, la mejora de la corriente oscura del sensor no es suficiente para nuestro
propósito. Para una mayor mejora del rango dinámico se deben incluir circuitos dentro del píxel.
No obstante, las tecnologías CIS usualmente no permiten nada más que transistores NMOS al
lado del fotosensor, lo cual implica una seria restricción en el circuito a usar. Como resultado, el
diseño de un sensor de imagen con mejora del rango dinámico en tecnologías CIS fue
desestimado en favor del uso de una tecnología estándar, la cual da más flexibilidad al diseño
del píxel.
En tecnologías estándar, es posible introducir una alta funcionalidad usando circuitos
dentro del píxel, lo cual permite técnicas avanzadas para extender el límite de saturación de los
sensores de imagen. Para este objetivo surgen dos opciones: adquisición lineal o compresiva. Si
se realiza una adquisición lineal, se generarán una gran cantidad de datos por cada píxel. Como
ejemplo, si el rango dinámico de la escena es de 120dB al menos se necesitarían 20-bits/píxel,
log2(10120/20)=19.93, para la representación binaria de este rango dinámico. Esto necesitaría de
amplios recursos para procesar esta gran cantidad de datos, y un gran ancho de banda para
moverlos al circuito de procesamiento. Para evitar estos problemas, los sensores de imagen de
alto rango dinámico usualmente optan por utilizar una adquisición compresiva de la luz. Por lo
tanto, esto implica dos tareas a realizar: la captura y la compresión de la imagen. La captura de
la imagen se realiza a nivel de píxel, en el dispositivo fotosensor, mientras que la compresión de
la imagen puede ser realizada a nivel de píxel, de sistema, o mediante postprocesado externo.
Usando el postprocesado, existe un campo de investigación que estudia la compresión de
escenas de alto rango dinámico mientras se mantienen los detalles, produciendo un resultado
apropiado para la percepción humana en monitores convencionales de bajo rango dinámico.
Esto se denomina Mapeo de Tonos (Tone Mapping) y usualmente emplea solo 8-bits/píxel para
las representaciones de imágenes, ya que éste es el estándar para las imágenes de bajo rango
dinámico.
Los píxeles de adquisición compresiva, por su parte, realizan una compresión que no es
dependiente de la escena de alto rango dinámico a capturar, lo cual implica una baja compresión
o pérdida de detalles y contraste. Para evitar estas desventajas, en este trabajo, se presenta un
píxel de adquisición compresiva que aplica una técnica de mapeo de tonos que permite la
captura de imágenes ya comprimidas de una forma optimizada para mantener los detalles y el
contraste, produciendo una cantidad muy reducida de datos. Las técnicas de mapeo de tonos
ejecutan normalmente postprocesamiento mediante software en un ordenador sobre imágenes
capturadas sin compresión, las cuales contienen una gran cantidad de datos. Estas técnicas han
pertenecido tradicionalmente al campo de los gráficos por ordenador debido a la gran cantidad
de esfuerzo computacional que requieren. Sin embargo, hemos desarrollado un nuevo algoritmo
de mapeo de tonos especialmente adaptado para aprovechar los circuitos dentro del píxel y que
requiere un reducido esfuerzo de computación fuera de la matriz de píxeles, lo cual permite el
desarrollo de un sistema de visión en un solo chip. El nuevo algoritmo de mapeo de tonos, el
cual es un concepto matemático que puede ser simulado mediante software, se ha implementado
también en un chip. Sin embargo, para esta implementación hardware en un chip son necesarias
algunas adaptaciones y técnicas avanzadas de diseño, que constituyen en sí mismas otra de las
contribuciones de este trabajo. Más aún, debido a la nueva funcionalidad, se han desarrollado
modificaciones de los típicos métodos a usar para la caracterización y captura de imágenes
Digital CMOS ISFET architectures and algorithmic methods for point-of-care diagnostics
Over the past decade, the surge of infectious diseases outbreaks across the globe is redefining how healthcare is provided and delivered to patients, with a clear trend towards distributed diagnosis at the Point-of-Care (PoC). In this context, Ion-Sensitive Field Effect Transistors (ISFETs) fabricated on standard CMOS technology have emerged as a promising solution to achieve a precise, deliverable and inexpensive platform that could be deployed worldwide to provide a rapid diagnosis of infectious diseases. This thesis presents advancements for the future of ISFET-based PoC diagnostic platforms, proposing and implementing a set of hardware and software methodologies to overcome its main challenges and enhance its sensing capabilities.
The first part of this thesis focuses on novel hardware architectures that enable direct integration with computational capabilities while providing pixel programmability and adaptability required to overcome pressing challenges on ISFET-based PoC platforms. This section explores oscillator-based ISFET architectures, a set of sensing front-ends that encodes the chemical information on the duty cycle of a PWM signal. Two initial architectures are proposed and fabricated in AMS 0.35um, confirming multiple degrees of programmability and potential for multi-sensing. One of these architectures is optimised to create a dual-sensing pixel capable of sensing both temperature and chemical information on the same spatial point while modulating this information simultaneously on a single waveform. This dual-sensing capability, verified in silico using TSMC 0.18um process, is vital for DNA-based diagnosis where protocols such as LAMP or PCR require precise thermal control.
The COVID-19 pandemic highlighted the need for a deliverable diagnosis that perform nucleic acid amplification tests at the PoC, requiring minimal footprint by integrating sensing and computational capabilities. In response to this challenge, a paradigm shift is proposed, advocating for integrating all elements of the portable diagnostic platform under a single piece of silicon, realising a ``Diagnosis-on-a-Chip". This approach is enabled by a novel Digital ISFET Pixel that integrates both ADC and memory with sensing elements on each pixel, enhancing its parallelism. Furthermore, this architecture removes the need for external instrumentation or memories and facilitates its integration with computational capabilities on-chip, such as the proposed ARM Cortex M3 system.
These computational capabilities need to be complemented with software methods that enable sensing enhancement and new applications using ISFET arrays. The second part of this thesis is devoted to these methods. Leveraging the programmability capabilities available on oscillator-based architectures, various digital signal processing algorithms are implemented to overcome the most urgent ISFET non-idealities, such as trapped charge, drift and chemical noise. These methods enable fast trapped charge cancellation and enhanced dynamic range through real-time drift compensation, achieving over 36 hours of continuous monitoring without pixel saturation.
Furthermore, the recent development of data-driven models and software methods open a wide range of opportunities for ISFET sensing and beyond. In the last section of this thesis, two examples of these opportunities are explored: the optimisation of image compression algorithms on chemical images generated by an ultra-high frame-rate ISFET array; and a proposed paradigm shift on surface Electromyography (sEMG) signals, moving from data-harvesting to information-focused sensing. These examples represent an initial step forward on a journey towards a new generation of miniaturised, precise and efficient sensors for PoC diagnostics.Open Acces
The ALICE Silicon Pixel Detector Control and Calibration Systems
The work presented in this thesis was carried out in the Silicon Pixel Detector (SPD) group of the ALICE experiment at the Large Hadron Collider (LHC). The SPD is the innermost part (two cylindrical layers of silicon pixel detec- tors) of the ALICE Inner Tracking System (ITS). During the last three years I have been strongly involved in the SPD hardware and software development, construction and commissioning. This thesis is focused on the design, development and commissioning of the SPD Control and Calibration Systems. I started this project from scratch. After a prototyping phase now a stable version of the control and calibration systems is operative. These systems allowed the detector sectors and half-barrels test, integration and commissioning as well as the SPD commissioning in the experiment. The integration of the systems with the ALICE Experiment Control System (ECS), DAQ and Trigger system has been accomplished and the SPD participated in the experimental December 2007 commissioning run. The complexity of the detectors, the high number of subcomponents and the harsh working environment make necessary the development of a control system parallel to the data acquisition. This online slow control, called Detector Control System (DCS), has the task of controlling and monitoring all hardware and software components of the detector and of the necessary infrastructures. The latter include the power distribution system, cool ing, interlock system, etc. In this scenario, the DCS assumes a key role. Its functionalities have extended well over the simple control and monitoring of the experiment. DCS, nowadays, are highly advanced and automated online data acquisition systems, with less stringent requirements compared to the DAQ. Moreover the SPD DCS has the unique feature of not only controlling but also operating the SPD front-end electronics. These requirements impose a high level of synchronization between the system components and a fast system response. The DCS, in this case, is a fundamental component for the detector calibration. The SPD DCS should be operated in the ALICE DCS framework hence a series of integration constraint should be applied to the system. Furthermore, in complex experiments such as ALICE, the detector operation is tightly bound to the connection and integration of the various systems such as DAQ, DCS, trigger system, Experiment Control System (ECS) and Offline framework. The operation of the SPD front-end electronics and services should be done at various levels of integration. At the first and bottom level it is required that each system runs safely and independently. At the second level the subsystem controls should be merged to form a unique entity. At this stage the components operation should be synchronized to reach the full detector operation. The third level requires the integration of the SPD control in the genera l ALICE DCS/ECS. These requirements have been fulfilled by designing the DCS with two main software layers. On the bottom a Supervisory Control And Data Acquisition (SCADA) layer controls and monitors the equipments. It is based on a commercial application, PVSS, and it also responsible of provide an user interface to the subsystem components. On top a Finite State Machine (FSM) Layer performs the logical connection between the SPD subsystems and it connects the SPD DCS with the ALICE DCS and ECS. PVSS is designed for slow control applications and it is not suitable for the direct control of the fast SPD front-end electronics. I designed a Front-End Device Server (FED Server) to interface the SCADA layer with the front-end electronics. The server receives macro-instructions from the SCADA and it operates autonomously the complex front-end electronics. The complexity of the detector calibration requires a high automation level and the integration of the calibration system with the ALICE calibration framework. In order to satisfy these requirements and provide the user with a simple and versatile interface, I decided to foresee two calibration scenarios. A calibration scenario, named DAQ ACTIVE, allows the fast detector calibration but it needs the control of the full detector and subsystems. A second calibration scenario, named DCS ONLY, slower than the DAQ ACTIVE scenario, allows the calibration of a detector partition without interference with the normal detector operation. The control and calibration systems have been used to characterize and test the SPD components before and after the integration in the detector, both in laboratory (DSF) and in the ALICE environment. Some calibration and control systems application examples as well as a brief overview of the detector performance evaluated during the commissioning phases are reported
A low-voltage CMOS-compatible time-domain photodetector, device & front end electronics
During the last decades, the usage of silicon photodetectors, both as stand-alone sensor or integrated in arrays, grew tremendously. They are now found in almost any application and any market range, from leisure products to high-end scientific apparatuses, including, among others, industrial, automotive, and medical equipment. The impressive growth in photodetector applications is closely linked to the development of CMOS technology, which now offers inexpensive and efficient analog and digi-tal signal processing capabilities. Detectors are often integrated with their respective front end and application-specific digital circuit on the same silicon die, forming complete systems on chip. In some cases the detector itself is not on the same chip but often part of the same package. However, this trend of co-integration of analog front end and digital circuits complicates the design of the analog part. The ever-decreasing supply voltage and the smaller transistors in advanced processes (which are driven by the development of digital cir-cuits) negatively impact the performance of the analog structures and complicates their design. For photodetector systems, the effect most importantly translates into a degradation of dynamic range and signal-to-noise ratio. One way to circumvent the problem of low supply voltages is to shift the operation from voltage domain to time domain. By doing so, the signal is no longer constrained by the supply rails and analog amplification is avoided. The signal takes the form of a time-based modulation, such as pulse-width modulation or pulse-frequency modulation. Another advantage is that the output signal of a time-domain photodetection system is directly interfaceable with digital circuits. In this work, a new type of CMOS-compatible photodetector displaying intrinsic light-to-time conversion is proposed. Its physical structure consists of a MOS gate interleaved with a PN junction. The MOS structure is acting as a photogate. The depletion region shrinks when photogenerated carriers fill the potential well. At some point, the anode of the PN structure is de-isolated from the rest of the detector and triggers a positive-feedback effect that leads to a very steep current increase through the PN-junction. This translates into a signal of very high amplitude and independent from light-intensity, which can be almost directly interfaced with digital circuits. This simplifies the front end circuit compared to photodiode-based systems. The physical behavior of the device is analyzed with the help of TCAD simulations and simple behavioral and shot-noise models are proposed. The device has been co-integrated with its driver and front end circuit in a standard CMOS process and its characteristics have been measured with a custom-made measurement system. The effect of bias parameters on the performance of the sensor are also analyzed. The limitations of the device are discussed, the most important ones being dark current and linearity. Techno-logical solutions, such as the implementation of the detector on Silicon-on-Insulator technology, are proposed to overcome the limitations. Finally, some application demonstrators have been realized. Other applications that could benefit from the detector are suggested, such as digital applications taking advantage of the latching behavior of the device, and a Photoplethysmography (PPG) system that uses a PLL-based control loop to minimize the emitting LED-current
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