Tunable n-path notch filters for blocker suppression: modeling and verification

N-path switched-RC circuits can realize filters with very high linearity and compression point while they are tunable by a clock frequency. In this paper, both differential and single-ended N-path notch filters are modeled and analyzed. Closed-form equations provide design equations for the main filtering characteristics and nonidealities such as: harmonic mixing, switch resistance, mismatch and phase imbalance, clock rise and fall times, noise, and insertion loss. Both an eight-path single-ended and differential notch filter are implemented in 65-nm CMOS technology. The notch center frequency, which is determined by the switching frequency, is tunable from 0.1 to 1.2 GHz. In a 50- environment, the N-path filters provide power matching in the passband with an insertion loss of 1.4–2.8 dB. The rejection at the notch frequency is 21–24 dB,P1 db> + 2 dBm, and IIP3 > + 17 dBm

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current

Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections

Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio

A discrete-time (DT) mixing architecture for RF-sampling receivers is presented. This architecture makes RF sampling more suitable for software-defined radio (SDR) as it achieves wideband quadrature demodulation and wideband harmonic rejection. The paper consists of two parts. In the first part, different downconversion techniques are classified and compared, leading to the definition of a DT mixing concept. The suitability of CT-mixing and RF-sampling receivers to SDR is also discussed. In the second part, we elaborate the DT-mixing architecture, which can be realized by de-multiplexing. Simulation shows a wideband 90° phase shift between I and Q outputs without systematic channel bandwidth limitation. Oversampling and harmonic rejection relaxes RF pre-filtering and reduces noise and interference folding. A proof-of-concept DT-mixing downconverter has been built in 65 nm CMOS, for 0.2 to 0.9 GHz RF band employing 8-times oversampling. It can reject 2nd to 6th harmonics by 40 dB typically and without systematic channel bandwidth limitation. Without an LNA, it achieves a gain of -0.5 to 2.5 dB, a DSB noise figure of 18 to 20 dB, an IIP3 = +10 dBm, and an IIP2 = +53 dBm, while consuming less than 19 mW including multiphase clock generation