On chip interconnects for multiprocessor turbo decoding architectures

International audienc

Configurable and Scalable Turbo Decoder for 4G Wireless Receivers

The increasing requirements of high data rates and quality of service (QoS) in fourth-generation (4G) wireless communication require the implementation of practical capacity approaching codes. In this chapter, the application of Turbo coding schemes that have recently been adopted in the IEEE 802.16e WiMax standard and 3GPP Long Term Evolution (LTE) standard are reviewed. In order to process several 4G wireless standards with a common hardware module, a reconfigurable and scalable Turbo decoder architecture is presented. A parallel Turbo decoding scheme with scalable parallelism tailored to the target throughput is applied to support high data rates in 4G applications. High-level decoding parallelism is achieved by employing contention-free interleavers. A multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. A new on-line address generation technique is introduced to support multiple Turbo interleaving patterns, which avoids the interleaver address memory that is typically necessary in the traditional designs. Design trade-offs in terms of area and power efficiency are analyzed for different parallelism and clock frequency goals

Application of a design space exploration tool to enhance interleaver generation

This paper presents a methodology to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs a C description of Input/Output data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a Resource Constraints Graph (RCG). Design space exploration is then performed through associated tools, to synthesize a STAR component under time-to-market constraints. The proposed approach has been tested to design an industrial data mixing block example: an Ultra-Wideband interleaver

(SI10-062) Comprehensive Study on Methodology of Orthogonal Interleavers

Interleaving permutes the data bits by employing a user defined sequence to reduce burst error which at times exceeds the minimum hamming distance. It serves as the sole medium to distinguish user data in the overlapping channel and is the heart of Interleave Division Multiple Access (IDMA) scheme. Versatility of interleavers relies on various design parameters such as orthogonality, correlation, latency and performance parameters like bit error rate (BER), memory occupancy and computation complexity. In this paper, a comprehensive study of interleaving phenomenon and discussion on numerous interleavers is presented. Also, the BER performance of interleavers using IDMA scheme is displayed

Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures

This work proposes a general framework for the design and simulation of network on chip based turbo decoder architectures. Several parameters in the design space are investigated, namely the network topology, the parallelism degree, the rate at which messages are sent by processing nodes over the network and the routing strategy. The main results of this analysis are: i) the most suited topologies to achieve high throughput with a limited complexity overhead are generalized de-Bruijn and generalized Kautz topologies; ii) depending on the throughput requirements different parallelism degrees, message injection rates and routing algorithms can be used to minimize the network area overhead.Comment: submitted to IEEE Trans. on Circuits and Systems I (submission date 27 may 2009

A Novel Seed Based Random Interleaving for OFDM System and Its PHY Layer Security Implications

Wireless channels are characterized by multipath and fading that can often cause long burst of errors. Even though, to date, many very sophisticated error correcting codes have been designed, yet none can handle long burst of errors efficiently. An interleaver, a device that distributes a burst of errors, possibly caused by a deep fade, and makes them appear as simple random errors, therefore, proves to a very useful technique when used in conjunction with an efficient error correcting code. In this work, a novel near optimal seed based random interleaver is designed. An optimal interleaver scatters a given burst of errors uniformly over a fixed block of data - a property that is measured by so called ‘spread’. The design makes use of a unique seed based pseudo-random sequence generator or logistic map based chaotic sequence generator to scramble the given block of data. Since the proposed design is based on a seed based scrambler, the nature of input is irrelevant. Therefore, the proposed interleaver can interleave either the bits or the symbols or the packets or even the frames. Accordingly, in this work, we analyze the suitability of interleaver when introduced before or after the modulation in single carrier communication systems and show that interleaving the bits before modulation or interleaving the symbols after modulation has same advantage. We further show that, in an orthogonal frequency division multiplexing (OFDM) systems, the position of interleaver, whether before or after constellation mapper, has no significance, and is interchangeable. However, scrambling symbols is computationally less expensive than scrambling bits. For the purpose of analyzing the performance of the proposed seed based random interleaver, simulations are carried out in MATLAB®. Results show that our proposed seed based random interleaver has near optimal properties of ‘spread’ and ‘dispersion’. Furthermore, the proposed interleaver is evaluated in terms of bit error rate (BER) versus length of burst error in a single carrier system both before and after modulation. The proposed interleaver out-performs the built in RANDINTLV in MATLAB® when used in the same system. It shows that proposed interleaver can convert greater amount of burst errors into simple random errors than that of MATLAB® interleaver. The proposed interleaver is also tested in IEEE 802.16e based WiMAX system with Stanford University Interim (SUI) channels to compare the performance of average BER versus SNR for both pre modulation and post modulation interleaver. Results show that pre modulation interleaver and post modulation has same performance. There is also a side advantage of this seed based interleaver, in that it generates a variety of unique random-looking interleaving sequences. Only a receiver that has the knowledge of the input seed can generate this sequence and no one else. If the interleaving patterns are kept secure then it can possibly be used to introduce an extra layer of security at physical (PHY) layer. In that way, at PHY layer, one builds an additional entry barrier to break through and it comes with no extra cost. This property has been investigated by carrying out key sensitivity analysis to show that the attacks to guess key can be very futile, as difference at 4th decimal place in the initial condition can lead to entirely different scrambling