Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

Adaptive design of delta sigma modulators

In this thesis, a genetic algorithm based on differential evolution (DE) is used to generate delta sigma modulator (DSM) noise transfer functions (NTFs). These NTFs outperform those generated by an iterative approach described by Schreier and implemented in the delsig Matlab toolbox. Several lowpass and bandpass DSMs, as well as DSM\u27s designed specifically for and very low intermediate frequency (VLIF) receivers are designed using the algorithm developed in this thesis and compared to designs made using the delsig toolbox. The NTFs designed using the DE algorithm always have a higher dynamic range and signal to noise ratio than those designed using the delsig toolbox

Simulation-based high-level synthesis of Nyquist-rate data converters using MATLAB/SIMULINK

This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB®. The embedded simulator uses SIMULINK® C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time up to 2 orders of magnitude as compared with previous approaches - based on the use of SIMULINK® elementary blocks. Moreover, S-functions are more suitable for implementing a more detailed description of the circuit. For all subcircuits, the accuracy of the behavioral models has been verified by electrical simulation using HSPICE. For synthesis purposes, the simulator is used for performance evaluation and combined with an hybrid optimizer for design parameter selection. The optimizer combines adaptive statistical optimization algorithm inspired in simulated annealing with a design-oriented formulation of the cost function. It has been integrated in the MATLAB/SIMULINK® platform by using the MATLAB® engine library, so that the optimization core runs in background while MATLAB® acts as a computation engine. The implementation on the MATLAB® platform brings numerous advantages in terms of signal processing, high flexibility for tool expansion and simulation with other electronic subsystems. Additionally, the presented toolbox comprises a friendly graphical user interface to allow the designer to browse through all steps of the simulation, synthesis and post-processing of results. In order to illustrate the capabilities of the toolbox, a 0.13)im CMOS 12bit@80MS/s analog front-end for broadband power line communications, made up of a pipeline ADC and a current steering DAC, is synthesized and high-level sized. Different experiments show the effectiveness of the proposed methodology.Ministerio de Ciencia y Tecnología TIC2003-02355RAICONI

Feedback Acquisition and Reconstruction of Spectrum-Sparse Signals by Predictive Level Comparisons

In this letter, we propose a sparsity promoting feedback acquisition and reconstruction scheme for sensing, encoding and subsequent reconstruction of spectrally sparse signals. In the proposed scheme, the spectral components are estimated utilizing a sparsity-promoting, sliding-window algorithm in a feedback loop. Utilizing the estimated spectral components, a level signal is predicted and sign measurements of the prediction error are acquired. The sparsity promoting algorithm can then estimate the spectral components iteratively from the sign measurements. Unlike many batch-based Compressive Sensing (CS) algorithms, our proposed algorithm gradually estimates and follows slow changes in the sparse components utilizing a sliding-window technique. We also consider the scenario in which possible flipping errors in the sign bits propagate along iterations (due to the feedback loop) during reconstruction. We propose an iterative error correction algorithm to cope with this error propagation phenomenon considering a binary-sparse occurrence model on the error sequence. Simulation results show effective performance of the proposed scheme in comparison with the literature

Sigma-Delta modulation based distributed detection in wireless sensor networks

We present a new scheme of distributed detection in sensor networks using Sigma-Delta modulation. In the existing works local sensor nodes either quantize the observation or directly scale the analog observation and then transmit the processed information independently over wireless channels to a fusion center. In this thesis we exploit the advantages of integrating modulation as a local processor into sensor design and propose a novel mixing topology of parallel and serial configurations for distributed detection system, enabling each sensor to transmit binary information to the fusion center, while preserving the analog information through collaborative processing. We develop suboptimal fusion algorithms for the proposed system and provide both theoretical analysis and various simulation results to demonstrate the superiority of our proposed scheme in both AWGN and fading channels in terms of the resulting detection error probability by comparison with the existing approaches

Identification of a one-bit lowpass sigma-delta modulator using BIMBO

International audienceWe show how the BIMBO identification method can be used for the online identification of the digital filter in a sigma-delta modulator's loop. This parameter estimation method only requires the knowledge of the bit stream at the modulator output. This approach does not rely on an approximation of the comparator (such as additive white noise or describing function approximation). Moreover, it requires no amplitude measurement, as opposed to most other methods, and, thus, it involves no additional electronics and it is therefore very economical to implement it practically. The method is described from a theoretical point of view and an experimental validation is given

Error modeling, self-calibration and design of pipelined analog to digital converters

Typescript (photocopy).As the field of signal processing accelerates toward the use of high performance digital techniques, there is a growing need for increasingly fast and accurate analog to digital converters. Three highly visible examples of this trend originated in the last decade. The advent of the compact disc revolutionized the way high-fidelity audio is stored, reproduced, recorded and processed. Digital communication links, fiber optic cables and in the near future ISDN networks (Integrated Services Digital Network) are steadily replacing major portions of telephone systems. Finally, video-conferencing, multi-media computing and currently emerging high definition television (HDTV) systems rely more and more on real-time digital data compression and image enhancing techniques. All these applications rely on analog to digital conversion. In the field of digital audio, the required conversion accuracy is high, but the conversion speed limited (16 bits, 2 x 20 kHz signal bandwidth). In the field of image processing, the required accuracy is less, but the data conversion speed high (8-10 bits, 5-20MHz bandwidth). New applications keep pushing for increasing conversion rates and simultaneously higher accuracies. This dissertation discusses new analog to digital converter architectures that could accomplish this. As a consequence of the trend towards digital processing, prominent analog designers throughout the world have engaged in very active research on the topic of data conversion. Unfortunately, literature has not always kept up. At the time of this writing, it seemed rather difficult to find detailed fundamental publications about analog to digital converter design. This dissertation represents a modest attempt to remedy this situation. It is hoped that anyone with a back-ground in analog design could go through this work and pick up the fundamentals of converter operation, as well as a number of more advanced design techniques

Phase Retrieval From Binary Measurements

We consider the problem of signal reconstruction from quadratic measurements that are encoded as +1 or -1 depending on whether they exceed a predetermined positive threshold or not. Binary measurements are fast to acquire and inexpensive in terms of hardware. We formulate the problem of signal reconstruction using a consistency criterion, wherein one seeks to find a signal that is in agreement with the measurements. To enforce consistency, we construct a convex cost using a one-sided quadratic penalty and minimize it using an iterative accelerated projected gradient-descent (APGD) technique. The PGD scheme reduces the cost function in each iteration, whereas incorporating momentum into PGD, notwithstanding the lack of such a descent property, exhibits faster convergence than PGD empirically. We refer to the resulting algorithm as binary phase retrieval (BPR). Considering additive white noise contamination prior to quantization, we also derive the Cramer-Rao Bound (CRB) for the binary encoding model. Experimental results demonstrate that the BPR algorithm yields a signal-to- reconstruction error ratio (SRER) of approximately 25 dB in the absence of noise. In the presence of noise prior to quantization, the SRER is within 2 to 3 dB of the CRB