Programmable rate modem utilizing digital signal processing techniques

The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery

Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

Integration, implementation and testing of the X-Band SASAR II system

Includes abstract.Includes bibliographical references (leaves 122-123).This dissertation focuses on the integration, implementation and testing of the X-Band (9.3 GHz) South African Synthetic Aperture Radar project (SASAR II). The SASAR II system was divided into three main subsystems for design and implementation at M.Sc. level. The three main systems were the transmitter and frequency distribution unit (FDU), the receiver and the radar digital unit (RDU). Although all subsystems are separate units, the design process was a collaborative effort. The purpose of a synthetic aperture radar (SAR) is to provide high resolution images of extensive areas from airborne platforms operating from long ranges. The SASAR II project was born out of the success of its predecessor, SASAR, which was a VHF SAR commissioned in 2000. The SASAR II system is a wide bandwidth X-Band radar system with a high resolution of 2x2m. The processed resolution of the SASAR II system is enhanced through design improvements of the transmitted bandwidth, pulse coding and the overall system coherency. The purpose of this dissertation is to verify the original design specifications of the system and to test its integrity when all subsystems are combined. The critical parameters for monitoring and testing are the power budget levels for each RF unit. An insufficient input drive for a mixer may result in a null output. Conversely a high input drive will result in the saturation of the device and the generation of intermodulation products and higher conversion losses. Testing of the digital pulse generator (DPG), which is part of the RDU, showed a drop in the specified output power of 10 dB. The power budget calculations made for the transmitter were made based on the input power of the DPG. The DPG unit also failed to provide adequate port to port isolation between the input trigger and the I & Q output channels. Spurious harmonics signals from the trigger resulted in aliasing with the IF frequencies. An extra filtering stage was added at the front end to isolate these harmonics. The sensitivity time control (STC) and the manual gain control (MGC) form the final amplification/attenuation stages of the receiver unit. The combination of the two units results in final output signal amplitudes of between 2.15 dBm and 32.5 dBm. The specified maximum input power of the ADC is 10 dBm. The additional gain stages in the MGC would drive the ADC into saturation and possibly result in permanent damage. The testing of the receiver and the ADC was therefore limited to low power testing. The complete system response closely matched that of the design specification. The sources of the spurious signals described in the previous dissertations were isolated and filtered out. This however required the use of pulsed RF measurement techniques, specifically regarding the use of the pulse desensitization factor (PDF). Since the tested signals have a PRF, the measurement equipment takes an average of the peak pulse power distributed over all the spectral components over a given PRI. The PDF therefore compensates for the drop in signal power

The Allen Telescope Array: The First Widefield, Panchromatic, Snapshot Radio Camera for Radio Astronomy and SETI

The first 42 elements of the Allen Telescope Array (ATA-42) are beginning to deliver data at the Hat Creek Radio Observatory in Northern California. Scientists and engineers are actively exploiting all of the flexibility designed into this innovative instrument for simultaneously conducting surveys of the astrophysical sky and conducting searches for distant technological civilizations. This paper summarizes the design elements of the ATA, the cost savings made possible by the use of COTS components, and the cost/performance trades that eventually enabled this first snapshot radio camera. The fundamental scientific program of this new telescope is varied and exciting; some of the first astronomical results will be discussed.Comment: Special Issue of Proceedings of the IEEE: "Advances in Radio Telescopes", Baars,J. Thompson,R., D'Addario, L., eds, 2009, in pres

Design of a Compact Electromyograph Data Acquisition System

Our team set out to design and prototype a compact electromyography (EMG) device that measures and records electrical signals associated with muscle activity. The EMG device designed in this project begins at the electrode assembly, where input signals from the muscles are amplified. The signal is transmitted to a central signal processing electrical board. The signal enters a filtering stage before being digitized by an analog to digital converter. The microcontroller is responsible for receiving, processing, and sending the digital signal, which is converted from the microcontroller’s UART communication to serial USB format and sent to a computer through a USB communication cable. Using MATLAB, the signal data can be transferred into a computer platform to be used in other applications