Design and analysis of a scalable terabit multicast packet switch : architecture and scheduling algorithms

Internet growth and success not only open a primary route of information exchange for millions of people around the world, but also create unprecedented demand for core network capacity. Existing switches/routers, due to the bottleneck from either switch architecture or arbitration complexity, can reach a capacity on the order of gigabits per second, but few of them are scalable to large capacity of terabits per second. In this dissertation, we propose three novel switch architectures with cooperated scheduling algorithms to design a terabit backbone switch/router which is able to deliver large capacity, multicasting, and high performance along with Quality of Service (QoS). Our switch designs benefit from unique features of modular switch architecture and distributed resource allocation scheme. Switch I is a unique and modular design characterized by input and output link sharing. Link sharing resolves output contention and eliminates speedup requirement for central switch fabric. Hence, the switch architecture is scalable to any large size. We propose a distributed round robin (RR) scheduling algorithm which provides fairness and has very low arbitration complexity. Switch I can achieve good performance under uniform traffic. However, Switch I does not perform well for non-uniform traffic. Switch II, as a modified switch design, employs link sharing as well as a token ring to pursue a solution to overcome the drawback of Switch 1. We propose a round robin prioritized link reservation (RR+POLR) algorithm which results in an improved performance especially under non-uniform traffic. However, RR+POLR algorithm is not flexible enough to adapt to the input traffic. In Switch II, the link reservation rate has a great impact on switch performance. Finally, Switch III is proposed as an enhanced switch design using link sharing and dual round robin rings. Packet forwarding is based on link reservation. We propose a queue occupancy based dynamic link reservation (QOBDLR) algorithm which can adapt to the input traffic to provide a fast and fair link resource allocation. QOBDLR algorithm is a distributed resource allocation scheme in the sense that dynamic link reservation is carried out according to local available information. Arbitration complexity is very low. Compared to the output queued (OQ) switch which is known to offer the best performance under any traffic pattern, Switch III not only achieves performance as good as the OQ switch, but also overcomes speedup problem which seriously limits the OQ switch to be a scalable switch design. Hence, Switch III would be a good choice for high performance, scalable, large-capacity core switches

Novel techniques in large scaleable ATM switches

Bibliography: p. 172-178.This dissertation explores the research area of large scale ATM switches. The requirements for an ATM switch are determined by overviewing the ATM network architecture. These requirements lead to the discussion of an abstract ATM switch which illustrates the components of an ATM switch that automatically scale with increasing switch size (the Input Modules and Output Modules) and those that do not (the Connection Admission Control and Switch Management systems as well as the Cell Switch Fabric). An architecture is suggested which may result in a scalable Switch Management and Connection Admission Control function. However, the main thrust of the dissertation is confined to the cell switch fabric. The fundamental mathematical limits of ATM switches and buffer placement is presented next emphasising the desirability of output buffering. This is followed by an overview of the possible routing strategies in a multi-stage interconnection network. A variety of space division switches are then considered which leads to a discussion of the hypercube fabric, (a novel switching technique). The hypercube fabric achieves good performance with an O(N.log₂N)²) scaling. The output module, resequencing, cell scheduling and output buffering technique is presented leading to a complete description of the proposed ATM switch. Various traffic models are used to quantify the switch's performance. These include a simple exponential inter-arrival time model, a locality of reference model and a self-similar, bursty, multiplexed Variable Bit Rate (VBR) model. FIFO queueing is simple to implement in an ATNI switch, however, more responsive queueing strategies can result in an improved performance. An associative memory is presented which allows the separate queues in the ATM switch to be effectively logically combined into a single FIFO queue. The associative memory is described in detail and its feasibility is shown by laying out the Integrated Circuit masks and performing an analogue simulation of the IC's performance is SPICE3. Although optimisations were required to the original design, the feasibility of the approach is shown with a 15Ƞs write time and a 160Ƞs read time for a 32 row, 8 priority bit, 10 routing bit version of the memory. This is achieved with 2µm technology, more advanced technologies may result in even better performance. The various traffic models and switch models are simulated in a number of runs. This shows the performance of the hypercube which outperforms a Clos network of equivalent technology and approaches the performance of an ideal reference fabric. The associative memory leverages a significant performance advantage in the hypercube network and a modest advantage in the Clos network. The performance of the switches is shown to degrade with increasing traffic density, increasing locality of reference, increasing variance in the cell rate and increasing burst length. Interestingly, the fabrics show no real degradation in response to increasing self similarity in the fabric. Lastly, the appendices present suggestions on how redundancy, reliability and multicasting can be achieved in the hypercube fabric. An overview of integrated circuits is provided. A brief description of commercial ATM switching products is given. Lastly, a road map to the simulation code is provided in the form of descriptions of the functionality found in all of the files within the source tree. This is intended to provide the starting ground for anyone wishing to modify or extend the simulation system developed for this thesis

On-board B-ISDN fast packet switching architectures. Phase 1: Study

The broadband integrate services digital network (B-ISDN) is an emerging telecommunications technology that will meet most of the telecommunications networking needs in the mid-1990's to early next century. The satellite-based system is well positioned for providing B-ISDN service with its inherent capabilities of point-to-multipoint and broadcast transmission, virtually unlimited connectivity between any two points within a beam coverage, short deployment time of communications facility, flexible and dynamic reallocation of space segment capacity, and distance insensitive cost. On-board processing satellites, particularly in a multiple spot beam environment, will provide enhanced connectivity, better performance, optimized access and transmission link design, and lower user service cost. The following are described: the user and network aspects of broadband services; the current development status in broadband services; various satellite network architectures including system design issues; and various fast packet switch architectures and their detail designs

Future benefits and applications of intelligent on-board processing to VSAT services

The trends and roles of VSAT services in the year 2010 time frame are examined based on an overall network and service model for that period. An estimate of the VSAT traffic is then made and the service and general network requirements are identified. In order to accommodate these traffic needs, four satellite VSAT architectures based on the use of fixed or scanning multibeam antennas in conjunction with IF switching or onboard regeneration and baseband processing are suggested. The performance of each of these architectures is assessed and the key enabling technologies are identified

High-speed, economical design implementation of transit network router

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.Includes bibliographical references (p. 88-90).by Kazuhiro Hara.M.S

Dissecting the meiotic defects of Tex19.1-/- mouse spermatocytes

The maintenance of genomic stability through suppression of retrotransposon activity is vital for the avoidance of potentially mutagenic genomic disruption caused by retrotransposition. Germline development is a particularly important phase for retrotransposon silencing as retrotransposition events here have the potential for transmission to the entire embryo, threatening the health of offspring. A collection of germline genome defence genes are required for the suppression of retrotransposons in the developing germline of male mice (e.g. Tex19.1, Dazl, Mili, Miwi2, Gasz, Mov10l1, Mael, Dnmt3l), all of which trigger meiotic prophase arrest when mutated. I have analysed the meiotic defects which arise in Tex19.1-/- male mice to contribute to the understanding of the fundamental mechanisms required for successful completion of meiosis and to investigate the involvement of retrotransposon silencing in this process. The absence of TEX19.1 in male mice causes infertility; with failed chromosome synapsis in ~50% of pachytene nuclei and associated apoptosis, as well as individual univalent chromosomes in 67% of remaining nuclei progressing to metaphase I. Where studied, failed chromosome synapsis is a common feature of germline genome defence mutant spermatocytes. One aim of my studies has been to better understand the mechanism responsible for this failed chromosome synapsis. I have demonstrated that unlike Mael-/- spermatocytes, additional SPO11-independent DNA damage potentially attributable to retrotransposition is not detectable in Tex19.1-/- spermatocytes. Rather, the formation of meiotic DNA double strand breaks (DSBs) is dramatically reduced in early prophase to around 50%, resulting in a reduction in nuclear γH2AX signal, production of SPO11- oligonucleotide complexes and foci formation by early recombination proteins RPA, DMC1 and RAD51. Despite this early reduction, DSB frequency recovers to more normal levels shortly after in zygotene. I have shown that defective pairing of homologous chromosomes by meiotic recombination is likely responsible for the asynapsis previously reported. The initial reduction in DSB frequency could be sufficient to cause failed chromosome synapsis in this mutant, assuming that late-forming DSBs cannot participate effectively in promoting homologous pairing. Alternative hypotheses include altered positioning of DSBs in response to altered chromatin organisation relating to retrotransposon upregulation, misguiding the pairing of homologous chromosomes. Such a model of disruption could also extend to other germline genome defence mutants. I have demonstrated that despite successful pairing of homologous chromosomes in a sub-population of Tex19.1-/- spermatocytes, subsequent progression of these cells through pachytene is delayed. Numerous diverse features of progression are all delayed, including recombination, ubiquitination on autosomes and sex chromosomes, expression of the mid-pachytene marker H1t, and chromosome organisation. The delay identified is related to recombination therefore this feature is likely to stem from the initial defect in DSB formation early in prophase. While some delayed features are probably directly related to recombination, others are not. The coordinated delay observed may suggest the presence of a recombination-sensitive cell-cycle checkpoint operating to regulate progression through pachytene. My research has also aimed to establish the cause of elevated univalent chromosomes not connected by chiasmata in metaphase I Tex19.1-/- spermatocytes. I have demonstrated that that absence of chiasmata is not due to failed crossover formation between synapsed chromosomes. Rather, the frequent observation of individual unsynapsed chromosomes during crossover formation suggests that some spermatocytes with low-level asynapsis are leaking through meiotic checkpoints and are unable to form a crossover before reaching metaphase. Therefore, again this later meiotic defect appears to stem from the initial defect in meiotic DSB formation, the consequences of which vary widely in severity. Remarkably the unsynapsed chromosomes present during crossover formation include both sex chromosomes, and autosomes. Tolerance of an unsynapsed autosome from pachytene into metaphase is an unusual observation in mice and this observation may aid the understanding of spermato cyte quality control mechanisms during this progression. Together these findings have greatly advanced the understanding of the infertility incurred during meiosis in Tex19.1-/- male mice. These findings may also extend to benefit the understanding of other germline genome defence mutants. Diverse observations made during my investigations also reveal a potential system of coordinated progression through pachytene relating to meiotic recombination. The variable severity of the synapsis defects incurred in this mutant appears to have variable effects on spermatocyte survival and could also inform the understanding of meiotic checkpoint sensitivity

NASA Tech Briefs, May 1992

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