Breaking Instance-Independent Symmetries In Exact Graph Coloring

Code optimization and high level synthesis can be posed as constraint satisfaction and optimization problems, such as graph coloring used in register allocation. Graph coloring is also used to model more traditional CSPs relevant to AI, such as planning, time-tabling and scheduling. Provably optimal solutions may be desirable for commercial and defense applications. Additionally, for applications such as register allocation and code optimization, naturally-occurring instances of graph coloring are often small and can be solved optimally. A recent wave of improvements in algorithms for Boolean satisfiability (SAT) and 0-1 Integer Linear Programming (ILP) suggests generic problem-reduction methods, rather than problem-specific heuristics, because (1) heuristics may be upset by new constraints, (2) heuristics tend to ignore structure, and (3) many relevant problems are provably inapproximable. Problem reductions often lead to highly symmetric SAT instances, and symmetries are known to slow down SAT solvers. In this work, we compare several avenues for symmetry breaking, in particular when certain kinds of symmetry are present in all generated instances. Our focus on reducing CSPs to SAT allows us to leverage recent dramatic improvement in SAT solvers and automatically benefit from future progress. We can use a variety of black-box SAT solvers without modifying their source code because our symmetry-breaking techniques are static, i.e., we detect symmetries and add symmetry breaking predicates (SBPs) during pre-processing. An important result of our work is that among the types of instance-independent SBPs we studied and their combinations, the simplest and least complete constructions are the most effective. Our experiments also clearly indicate that instance-independent symmetries should mostly be processed together with instance-specific symmetries rather than at the specification level, contrary to what has been suggested in the literature

Experimental assessment of the productivity improvement when using U-shaped production cells with variable takt time

International audiencePurpose – The aims of this research is to discuss the benefits of U layout for production cell operating in variable takt time. Different experiments were conducted using benchmarks, in order to highlight the performance gap between a straight cell and a U-cell. Design/methodology/approach – The implementation of the production cell, in U-shaped or in straight line, is optimized through linear programming based on the number of operators. The two corresponding programs, in Mosel language, use the same approach, in order to not introduce defects in the comparison of results. The study used our own datasets and well known academic benchmarks. Findings – A comparison between the obtained takt times, with equivalent operating conditions, in U-cell and straight cell was conducted. A significant increase of the production rate was observed. This increase has often exceeded 10 per cent to reach 32 per cent. All the experiments show that, with the same number of operators, a cell in a U layout is always at least as efficient, in terms of reachable production rates, than an equivalent cell in a linear layout. 96 per cent give an improvement of production rate. Moreover, the dispersion of the U-cell results is weaker, which suggests that the U-layout gives, in more robust manner, better performances.Research limitations/implications – The results were obtained through a study of various academic benchmarks. The results must be validated on industrial situations.Practical implications – This paper will be very useful for researchers and practitioners in order to understand lean implementations and its derived benefits. This paper will allow them evaluating and analysing the expected benefits of the implementation of the production cell in U-shaped (operating in variable takt time).Originality/value – U-Cells constitute an appropriate solution for a layout of any kind of production cells with variable structure. When facing a significant variation in the demand, the response consists in modulating the number of operators assigned to the cell. This study addresses jointly the problem of U-cells layout and the operation in variable takt time

The Generic Checkout System Approach to Ground Checkout Systems

With the advent of the Space Station, Heavy Lift Launch Vehicle and other projects, NASA has been prompted to critique major ground checkout systems around KSC. This critique is being used as a basis for the development of a central set of functions which are common to all checkout operations throughout the program. A prototyping effort was started over a year ago to implement those central functions, this effort was called the Generic Checkout System(GCS) which, over the past year, has grown into a working model 1 for ground checkout systems. At the Twenty-Third Space Congress a paper was presented which outlined the rudimentary operations of the GCS. Since that time GCS has evolved into a state of the art checkout system which demonstrates flexibility and ease of use. The GCS system has been chosen as the architecture which will support the Partial Paylod Checkout Unit(PPCU), a new system to be installed in early 1990. The development of the GCS system was meant to also address several problems inherent in current checkout systems: lack of flexibility, poor user interfaces and the abscence of an upgrade path from obsolete hardware. The GCS seeks to solve these problems in ways which utilize high technology advances in computer hardware and software. These advances include the use of commercial UNIX operating system based computers which offer vendor independence and portability of software, the use of state of the art user interfaces offering high resolution graphics, mouse interfaces and the ability to create displays interactively without the need to generate code to drive them. The use of other high tech products is also apparent in the GCS such as the support for Artificial intelligence, relational data base technologies, ADA programming language, parallel processing, RISC technology architectures, optical storage media, Local Area Network Connectivity, commercial graphics packages, INMOS transputers and the latest microprocessor technologies. This paper will attempt to explore some of the facets of the GCS prototyping and development effort and mention the future plans for the architecture which has been developed

GeNN: a code generation framework for accelerated brain simulations

Large-scale numerical simulations of detailed brain circuit models are important for identifying hypotheses on brain functions and testing their consistency and plausibility. An ongoing challenge for simulating realistic models is, however, computational speed. In this paper, we present the GeNN (GPU-enhanced Neuronal Networks) framework, which aims to facilitate the use of graphics accelerators for computational models of large-scale neuronal networks to address this challenge. GeNN is an open source library that generates code to accelerate the execution of network simulations on NVIDIA GPUs, through a flexible and extensible interface, which does not require in-depth technical knowledge from the users. We present performance benchmarks showing that 200-fold speedup compared to a single core of a CPU can be achieved for a network of one million conductance based Hodgkin-Huxley neurons but that for other models the speedup can differ. GeNN is available for Linux, Mac OS X and Windows platforms. The source code, user manual, tutorials, Wiki, in-depth example projects and all other related information can be found on the project website http://genn-team.github.io/genn/

The role of the host in a cooperating mainframe and workstation environment, volumes 1 and 2

In recent years, advancements made in computer systems have prompted a move from centralized computing based on timesharing a large mainframe computer to distributed computing based on a connected set of engineering workstations. A major factor in this advancement is the increased performance and lower cost of engineering workstations. The shift to distributed computing from centralized computing has led to challenges associated with the residency of application programs within the system. In a combined system of multiple engineering workstations attached to a mainframe host, the question arises as to how does a system designer assign applications between the larger mainframe host and the smaller, yet powerful, workstation. The concepts related to real time data processing are analyzed and systems are displayed which use a host mainframe and a number of engineering workstations interconnected by a local area network. In most cases, distributed systems can be classified as having a single function or multiple functions and as executing programs in real time or nonreal time. In a system of multiple computers, the degree of autonomy of the computers is important; a system with one master control computer generally differs in reliability, performance, and complexity from a system in which all computers share the control. This research is concerned with generating general criteria principles for software residency decisions (host or workstation) for a diverse yet coupled group of users (the clustered workstations) which may need the use of a shared resource (the mainframe) to perform their functions

Developing a Benchmark for Evaluating the Performance of Parallel Computers

This paper discusses the development of a portable suite of benchmarking programs for parallel computers. Comparative measurement of the performance of parallel computing systems has been limited because of the great diversity of architectures and of processor interconnection schemes. One solution is to translate benchmark codes into a consistent and portable parallel language. This paper reports on progress in developing such a portable suite of benchmarks. An extensive introduction to parallel computing is included as an appendix, to provide a thorough understanding of the factors complicating development of the performance suite. Key to the development was the use of p4, a library of tools developed at Argonne National Laboratory. The benchmark codes were translated successfully using p4 and were run on a variety of parallel machines. Conclusions and suggestions for future work are given

High performance computing of explicit schemes for electrofusion jointing process based on message-passing paradigm

The research focused on heterogeneous cluster workstations comprising of a number of CPUs in single and shared architecture platform. The problem statements under consideration involved one dimensional parabolic equations. The thermal process of electrofusion jointing was also discussed. Numerical schemes of explicit type such as AGE, Brian, and Charlies Methods were employed. The parallelization of these methods were based on the domain decomposition technique. Some parallel performance measurement for these methods were also addressed. Temperature profile of the one dimensional radial model of the electrofusion process were also given

Assessment Report 2012 Russell Brands, Pakistan AA0000000108

This document is part of a digital collection provided by the Martin P. Catherwood Library, ILR School, Cornell University, pertaining to the effects of globalization on the workplace worldwide. Special emphasis is placed on labor rights, working conditions, labor market changes, and union organizing.FLA_2012_Russell_Brands_AR_Pakistan_AA0000000108.pdf: 57 downloads, before Oct. 1, 2020

An Experiment on Bare-Metal BigData Provisioning

Many BigData customers use on-demand platforms in the cloud, where they can get a dedicated virtual cluster in a couple of minutes and pay only for the time they use. Increasingly, there is a demand for bare-metal bigdata solutions for applications that cannot tolerate the unpredictability and performance degradation of virtualized systems. Existing bare-metal solutions can introduce delays of 10s of minutes to provision a cluster by installing operating systems and applications on the local disks of servers. This has motivated recent research developing sophisticated mechanisms to optimize this installation. These approaches assume that using network mounted boot disks incur unacceptable run-time overhead. Our analysis suggest that while this assumption is true for application data, it is incorrect for operating systems and applications, and network mounting the boot disk and applications result in negligible run-time impact while leading to faster provisioning time.This research was supported in part by the MassTech Collaborative Research Matching Grant Program, NSF awards 1347525 and 1414119 and several commercial partners of the Massachusetts Open Cloud who may be found at http://www.massopencloud.or