Source-synchronous I/O Links using Adaptive Interface Training for High Bandwidth Applications

Mobility is the key to the global business which requires people to be always connected to a central server. With the exponential increase in smart phones, tablets, laptops, mobile traffic will soon reach in the range of Exabytes per month by 2018. Applications like video streaming, on-demand-video, online gaming, social media applications will further increase the traffic load. Future application scenarios, such as Smart Cities, Industry 4.0, Machine-to-Machine (M2M) communications bring the concepts of Internet of Things (IoT) which requires high-speed low power communication infrastructures. Scientific applications, such as space exploration, oil exploration also require computing speed in the range of Exaflops/s by 2018 which means TB/s bandwidth at each memory node. To achieve such bandwidth, Input/Output (I/O) link speed between two devices needs to be increased to GB/s. The data at high speed between devices can be transferred serially using complex Clock-Data-Recovery (CDR) I/O links or parallely using simple source-synchronous I/O links. Even though CDR is more efficient than the source-synchronous method for single I/O link, but to achieve TB/s bandwidth from a single device, additional I/O links will be required and the source-synchronous method will be more advantageous in terms of area and power requirements as additional I/O links do not require extra hardware resources. At high speed, there are several non-idealities (Supply noise, crosstalk, Inter- Symbol-Interference (ISI), etc.) which create unwanted skew problem among parallel source-synchronous I/O links. To solve these problems, adaptive trainings are used in time domain to synchronize parallel source-synchronous I/O links irrespective of these non-idealities. In this thesis, two novel adaptive training architectures for source-synchronous I/O links are discussed which require significantly less silicon area and power in comparison to state-of-the-art architectures. First novel adaptive architecture is based on the unit delay concept to synchronize two parallel clocks by adjusting the phase of one clock in only one direction. Second novel adaptive architecture concept consists of Phase Interpolator (PI)-based Phase Locked Loop (PLL) which can adjust the phase in both direction and achieve faster synchronization at the expense of added complexity. With an increase in parallel I/O links, clock skew which is generated by the improper clock tree, also affects the timing margin. Incorrect duty cycle further reduces the timing margin mainly in Double Data Rate (DDR) systems which are generally used to increase the bandwidth of a high-speed communication system. To solve clock skew and duty cycle problems, a novel clock tree buffering algorithm and a novel duty cycle corrector are described which further reduce the power consumption of a source-synchronous system

Power-efficient high-speed interface circuit techniques

Inter- and intra-chip connections have become the new challenge to enable the scaling of computing systems, ranging from mobile devices to high-end servers. Demand for aggregate I/O bandwidth has been driven by applications including high-speed ethernet, backplane micro-servers, memory, graphics, chip-to-chip and network onchip. I/O circuitry is becoming the major power consumer in SoC processors and memories as the increasing bandwidth demands larger per-pin data rate or larger I/O pin count per component. The aggregate I/O bandwidth has approximately doubled every three to four years across a diverse range of standards in different applications. However, in order to keep pace with these standards enabled in part by process-technology scaling, we will require more than just device scaling in the near future. New energy-efficient circuit techniques must be proposed to enable the next generations of handheld and high-performance computers, given the thermal and system-power limits they start facing. ^ In this work, we are proposing circuit architectures that improve energy efficiency without decreasing speed performance for the most power hungry circuits in high speed interfaces. By the introduction of a new kind of logic operators in CMOS, called implication operators, we implemented a new family of high-speed frequency dividers/prescalers with reduced footprint and power consumption. New techniques and circuits for clock distribution, for pre-emphasis and for driver at the transmitter side of the I/O circuitry have been proposed and implemented. At the receiver side, new DFE architecture and CDR have been proposed and have been proven experimentally

CMOS Phase Modulator for Polar Transmitters

Wireless communications are developing quickly. The search for higher data rates is pushing the integration of wideband code-division multiple access (WCDMA) into Global System for Mobile Communications (GSM) and Enhanced Data Rates for GSM Evolution (EDGE) networks. A critical part of the wireless device is the radio transceiver which consists of a receiver and a transmitter. Wireless receivers typically depend on low-intermediate frequency (IF) and direct conversion architectures that convert the received signal directly to baseband frequencies. Wireless transmitters usually employ one of two popular architectures, direct up conversion or polar modulation.It is important to develop a transmitter with a high efficiency and linearity, and with a low system complexity. So, one of the greatest solution is the use of a polar transmitter. A polar transmitter is mainly constituted by two blocks which one is responsible for the phase modulator and the other one for the amplitude modulator. The aim of this dissertation is building a phase modulator for a polar transmitter. This modulator cannot be fully digitally because those architectures have a great power consumption due to the use of multiplexers with a significative number of inputs. Based on this, we decided to follow a mixed signal approach. This modulator is composed by three main blocks: a phase interpolator, a phase signal divider and a sign bit. The crucial cell of this project is the phase interpolator, which is responsible for performing the final RF phase modulation. It receives two digital differential orthogonal signals, thus those signals define which quadrant of unit-circle will be performed. Also, it receives a baseband signal which will select the output phase in the desired quadrant. To select the desired quadrant to perform it was developed a sign bit cell which is responsible for select the input signals of the interpolator. To obtain those four input RF signals it was used a frequency signal divider composed by latches which receive a signal with a frequency two times greater than the required. A high performance phase modulator must have a low phase noise , which implies an increase of power consumption. Based on this, the goal of this project was achieved a great phase resolution with a better power consumption without damaging the output phase per quadrant.In this project, it was achieved a 5-bit resolution, per quadrant, for 360uW power consumption

A GHz-range, High-resolution Multi-modulus Prescaler for Extreme Environment Applications

The generation of a precise, low-noise, reliable clock source is critical to developing mixed-signal and digital electronic systems. The applications of such a clock source are greatly expanded if the clock source can be configured to output different clock frequencies. The phase-locked loop (PLL) is a well-documented architecture for realizing this configurable clock source. Principle to the configurability of a PLL is a multi-modulus divider. The resolution of this divider (or prescaler) dictates the resolution of the configurable PLL output frequency. In integrated PLL designs, such a multi-modulus prescaler is usually sourced from a GHz-range voltage-controlled oscillator. Therefore, a fully-integrated PLL ASIC requires the development of a high-speed, high-resolution multi-modulus prescaler. The design challenges associated with developing such a prescaler are compounded when the application requires the device to operate in an extreme environment. In these extreme environments (often extra-terrestrial), wide temperature ranges and radiation effects can adversely affect the operation of electronic systems. Even more problematic is that extreme temperatures and ionizing radiation can cause permanent damage to electronic devices. Typical commercial-off-the-shelf (COTS) components are not able withstand such an environment, and any electronics operating in these extreme conditions must be designed to accommodate such operation. This dissertation describes the development of a high-speed, high-resolution, multi-modulus prescaler capable of operating in an extreme environment. This prescaler has been developed using current-mode logic (CML) on a 180-nm silicon-germanium (SiGe) BiCMOS process. The prescaler is capable of operating up to at least 5.4 GHz over a division range of 16-48 with a total of 27 configurable moduli. The prescaler is designed to provide excellent ionizing radiation hardness, single-event latch-up (SEL) immunity, and single-event upset (SEU) resistance over a temperature range of −180°C to 125°C

Wireless Testing of Integrated Circuits.

Integrated circuits (ICs) are usually tested during manufacture by means of automatic testing equipment (ATE) employing probe cards and needles that make repeated physical contact with the ICs under test. Such direct-contact probing is very costly and imposes limitations on the use of ATE. For example, the probe needles must be frequently cleaned or replaced, and some emerging technologies such as three-dimensional ICs cannot be probed at all. As an alternative to conventional probe-card testing, wireless testing has been proposed. It mitigates many of the foregoing problems by replacing probe needles and contact points with wireless communication circuits. However, wireless testing also raises new problems which are poorly understood such as: What is the most suitable wireless communication technique to employ, and how well does it work in practice? This dissertation addresses the design and implementation of circuits to support wireless testing of ICs. Various wireless testing methods are investigated and evaluated with respect to their practicality. The research focuses on near-field capacitive communication because of its efficiency over the very short ranges needed during IC manufacture. A new capacitive channel model including chip separation, cross-talk, and misalignment effects is proposed and validated using electro-magnetic simulation studies to provide the intuitions for efficient antenna and circuit design. We propose a compact clock and data recovery architecture to avoid a dedicated clock channel. An analytical model which predicts the DC-level fluctuation due to the capacitive channel is presented. Based on this model, feed-forward clock selection is designed to enhance performance. A method to select proper channel termination is discussed to maximize the channel efficiency for return-to-zero signaling. Two prototype ICs incorporating wireless testing systems were fabricated and tested with the proposed methods of testing digital circuits. Both successfully demonstrated gigahertz communication speeds with a bit-error rate less than 10^−11. A third prototype IC containing analog voltage measurement circuits was implemented to determine the feasibility of wirelessly testing analog circuits. The fabricated prototype achieved satisfactory voltage measurement with 1 mV resolution. Our work demonstrates the validity of the proposed models and the feasibility of near-field capacitive communication for wireless testing of ICs.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/93993/1/duelee_1.pd

Engineering evaluations and studies. Volume 3: Exhibit C

High rate multiplexes asymmetry and jitter, data-dependent amplitude variations, and transition density are discussed

A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

Study of modulation techniques for multiple access satellite communications

Multiple access communication utilizing small ground stations for satellite communication modulation - multiplexing technique

Synchronous meteorological satellite system description document, volume 4

The command and data acquisition (CDA) station for the Synchronous Meteorological Satellite (SMS) program, located on the Eastern shore of Virginia, is described in terms of facility layout, ground support instrumentation, and capabilities. Data systems and equipment are described in detailed block diagrams. The major subsystems are identified and information on equipment specifications, frequency ranges, and data processing format is given. Automatic picture transmission, data utilization stations, data collection platforms, and the various communication links from the CDA station to the SMS spacecraft are discussed