A Control-Bounded Quadrature Leapfrog ADC

In this paper, the design flexibility of the control-bounded analog-to-digital converter principle is demonstrated. A band-pass analog-to-digital converter is considered as an application and case study. We show how a low-pass control-bounded analog-to-digital converter can be translated into a band-pass version where the guaranteed stability, converter bandwidth, and signal-to-noise ratio are preserved while the center frequency for conversion can be positioned freely. The proposed converter is validated with behavioral simulations on several filter orders, center frequencies, and oversampling ratios. Additionally, we consider an op-amp circuit realization where the effects of first-order op-amp non-idealities are shown. Finally, robustness against component variations is demonstrated by Monte Carlo simulations.Comment: 13 pages and 16 figure

Low Power Continuous-time Bandpass Delta-Sigma Modulators.

Low power techniques for continuous-time bandpass delta-sigma modulators (CTBPDSMs) are introduced. First, a 800MS/s low power 4th-order CTBPDSM with 24MHz bandwidth at 200MHz IF is presented. A novel power-efficient resonator with a single amplifier is used in the loopfilter. A single op-amp resonator makes use of positive feedback to increase the quality factor. Also, a new 4th-order architecture is introduced for system simplicity and low power. Low power consumption and a simple modulator structure are achieved by reducing the number of feedback DACs. This modulator achieves 58dB SNDR, and the total power consumption is 12mW. Second, a 6th-order CTBPDSM with duty cycle controlled DACs is presented. This prototype introduces new architecture for low power consumption and other important features. Duty cycle control enables the use of a single DAC per resonator without degrading the signal transfer function (STF), and helps to lower power consumption, low area, and thermal noise. This ADC provides input signal filtering, and increases the dynamic range by reducing the peaking in the STF. Furthermore, the center frequency is tunable so that the CTBPDSM is more useful in the receiver. The prototype second modulator achieves 69dB SNDR, and consumes 35mW, demonstrating the best FoM of 320fJ/conv.-step for CTBPDSMs using active resonators. The techniques introduced in this research help CTBPDSMs have good power efficiency compared with the other kinds of ADCs, and make the implement of a software-defined radio architecture easier which is appropriate for the future multiple standard radio receivers without a power penalty.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98001/1/hichae_1.pd

Integrated Circuit Blocks for High Performance Baseband and RF Analog-to-Digital Converters

Nowadays, the multi-standard wireless receivers and multi-format video processors have created a great demand for integrating multiple standards into a single chip. The multiple standards usually require several Analog to Digital Converters (ADCs) with different specifications. A promising solution is adopting a power and area efficient reconfigurable ADC with tunable bandwidth and dynamic range. The advantage of the reconfigurable ADC over customized ADCs is that its power consumption can be scaled at different specifications, enabling optimized power consumption over a wide range of sampling rates and resulting in a more power efficient design. Moreover, the reconfigurable ADC provides IP reuse, which reduces design efforts, development costs and time to market. On the other hand, software radio transceiver has been introduced to minimize RF blocks and support multiple standards in the same chip. The basic idea is to perform the analog to digital (A/D) and digital to analog (D/A) conversion as close to the antenna as possible. Then the backend digital signal processor (DSP) can be programmed to deal with the digital data. The continuous time (CT) bandpass (BP) sigma-delta ADC with good SNR and low power consumption is a good choice for the software radio transceiver. In this work, a proposed 10-bit reconfigurable ADC is presented and the non-overlapping clock generator and state machine are implemented in UMC 90nm CMOS technology. The state machine generates control signals for each MDAC stage so that the speed can be reconfigured, while the power consumption can be scaled. The measurement results show that the reconfigurable ADC achieved 0.6-200 MSPS speed with 1.9-27 mW power consumption. The ENOB is about 8 bit over the whole speed range. In the second part, a 2-bit quantizer with tunable delay circuit and 2-bit DACs are implemented in TSMC 0.13um CMOS technology for the 4th order CT BP sigma-delta ADC. The 2-bit quantizer and 2-bit DACs have 6dB SNR improvement and better stability over the single bit quantizer and DACs. The penalty is that the linearity of the feedback DACs should be considered carefully so that the nonlinearity doesn't deteriorate the ADC performance. The tunable delay circuit in the quantizer is designed to adjust the excess loop delay up to +/- 10% to achieve stability and optimal performance

Design of a 125 mhz tunable continuous-time bandpass modulator for wireless IF applications

Bandpass sigma-delta modulators combine oversampling and noise shaping to get very high resolution in a limited bandwidth. They are widely used in applications that require narrowband high-resolution conversion at high frequencies. In recent years interests have been seen in wireless system and software radio using sigma-delta modulators to digitize signals near the front end of radio receivers. Such applications necessitate clocking the modulators at a high frequency (MHz or above). Therefore a loop filter is required in continuous-time circuits (e.g., using transconductors and integrators) rather than discretetime circuits (e.g., using switched capacitors) where the maximum clocking rate is limited by the bandwidth of Opamp, switchÂs speed and settling-time of the circuitry. In this work, the design of a CMOS fourth-order bandpass sigma-delta modulator clocking at 500 MHz for direct conversion of narrowband signals at 125 MHz is presented. A new calibration scheme is proposed for the best signal-to-noise-distortion-ratio (SNDR) of the modulator. The continuous-time loop filter is based on Gm-C resonators. A novel transconductance amplifier has been developed with high linearity at high frequency. Qfactor of filter is enhanced by tunable negative impedance which cancels the finite output impendence of OTA. The fourth-order modulator is implemented using 0.35 mm triplemetal standard analog CMOS technology. Postlayout simulation in CADENCE demonstrates that the modulator achieves a SNDR of 50 dB (~8 bit) performance over a 1 MHz bandwidth. The modulatorÂs power consumption is 302 mW from supply power of ± 1.65V

Bandpass electromechanical sigma-delta modulator

Ph.DDOCTOR OF PHILOSOPH

Transmitter architectures with digital modulators, D/A converters and switching-mode power amplifiers

This thesis is composed of nine publications and an overview of the research topic, which also summarises the work. The research described in this thesis focuses on research into the digitalisation of wireless communication base station transmitters. In particular it has three foci: digital modulation, D/A conversion and switching-mode power amplification. The main interest in the implementation of these circuits is in CMOS. The work summarizes the designs of several circuit blocks of a wireless transmitter base station. In the baseband stage, a multicarrier digital modulator that combines multiple modulated signals at different carrier frequencies digitally at baseband, and a multimode digital modulator that can be operated for three different communications standards, are implemented as integrated circuits. The digital modulators include digital power ramping and power level control units for transmission bursts. The upconversion of the baseband signal is implemented using an integrated digital quadrature modulator. The work presented provides insight into the digital-to-analogue interface in the transmitters. This interface is studied both by implementing an intermediate frequency D/A converter in BiCMOS technology and bandpass Delta-Sigma modulator-based D/A conversion in CMOS technology. Finally, the last part of the work discusses switching-mode power amplifiers which are experimented with both as discrete and integrated implementations in conjunction with 1-bit Delta-Sigma modulation and pulse-width modulation as input signal generation methods.Tämä väitöskirja koostuu yhdeksästä julkaisusta ja tutkimusaiheen yhteenvedosta. Väitöskirjassa esitetty tutkimus keskittyy langattaman viestinnän tukiasemien lähettimien digitalisoinnin tutkimukseen. Yksityiskohtaisemmin tutkimusalueet ovat: digitaalinen modulaatio, D/A muunnos ja kytkinmuotoiset tehovahvistimet. Näiden elektronisten piirien toteutuksessa keskitytään CMOS teknologiaan. Työ vetää yhteen useiden langattoman viestinnän tukiasemien lähettimien piirilohkojen suunnittelun. Kantataajuusasteella toteutetaan integroituna piirinä monikantoaaltoinen digitaalinen modulaattori, joka yhdistää useita moduloituja signaaleja eri kantoaalloilla digitaalisesti ja monistandardi digitaalinen modulaatori, joka tukee kolmea eri viestintästandardia. Digitaaliset modulaattoripiirit sisältävät digitaalisen tehoramping ja tehotason säätöyksikön lähetyspurskeita varten. Kantataajuussignaalin ylössekoitus toteutetaan integroitua digitaalista kvadratuurimodulaattoria käyttäen. Esitetty työ antaa näkemystä lähettimien digitalia-analogia rajapintaan, jota tutkitaan toteuttamalla välitaajuinen D/A muunnin BiCMOS teknologialla ja päästökaistainen Delta-Sigma-modulaattoripohjainen D/A muunnin CMOS teknologialla. Lopuksi työn viimeinen osa käsittelee kytkinmuotoisia tehovahvistimia, joita tutkitaan kokeellisesti sekä erilliskompontein toteutettuina piirein että integroiduin piirein toteutettuina käyttäen sisääntulosignaalin muodostamismenetemänä yksibittistä Delta-Sigma-modulaatiota ja pulssin leveys modulaatiota.reviewe

A survey on continuous-time modulators : theory, designs and implementations

Recently, delta-sigma modulation has become a widely applied technique for high-performance analog-to-digital conversion of narrow-band signals. Most of the early designs used discrete-time structure for good accuracy and good linearity. The transfer functions are independent of the clock frequency. However, high unity-gain bandwidths of the opamps are required to satisfy the settling accuracy required in the discrete-time designs. Continuous-time structure can potentially achieve higher clock frequency with less power consumption. the anti-aliasing filter can also be eliminated due to the anti-aliasing property of CT modulators. On the other hand, CT ADC have their own problems, such as jitter sensitivity and excess loop delay. In this thesis, the state-of-the-art of CT modulator is reviewed. The problems in the design of CT ADCs are analyzed and solutions to them are described. The theory, design and implementations of CT modulator will also be reviewed.Keywords: Continuous-Time, Delta-Sigm

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

Undersampling bandpass modulator architectures

Continuous-time delta sigma modulators -- Undersampling Delta-sigma modulators for radio receivers -- A novel continuous-time delta sigma modulator -- New delta modulator based on undersampling