3 research outputs found

    Study Of Nanoscale Cmos Device And Circuit Reliability

    Get PDF
    The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices from device level to circuit level; The more real voltage stress case high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future

    Development of a Universal MOSFET Gate Impedance Model

    Get PDF
    Scaling of CMOS technology to 100 nm & below and the endless pursuit of higher operating frequencies drive the need to accurately model effects that dominate at those feature sizes and frequencies. Current modeling techniques are frequency limited and require different models for different frequency ranges in order to achieve accuracy goals. In the foundry world, high frequency models are typically empirical in nature and significantly lag their low frequency counterparts in terms of availability. This tends to slow the adoption of new foundry technologies for high performance applications such as extremely high data rate serializer/deserializer transceiver cores. However, design cycle time and time to market while transitioning between technology nodes can be reduced by incorporating a reusable, industry-standard model. This work proposes such a model for device gate impedance that is simulator-friendly, compact, frequencyindependent, and relatively portable across technology nodes. This semi-empirical gate impedance model is based on depletion in the poly-silicon gate electrode. The effect of device length and single-leg width on the input impedance is studied with the aid of extensive measured data obtained from devices built in 110 nm and 180 nm technologies in the 1-20GHz frequency range. The measured data illustrates that the device input impedance has a non-linear frequency dependency. This variation in input impedance is the result of gate poly-silicon depletion, which can be modeled by an external RC network connected at the gate of the device. Excellent agreement between the simulation results and the measured data validates the model in the device active region for 1-20GHz frequency range. The gate impedance model is further modified by incorporating parasitic effects, extending its range to 200MHz-20GHz. This model performs accurately for 180 run, 110 nm and 90 nm technologies at different bias conditions and dimensions. The model and model parameter behavior are consistent across technology nodes thereby enabling re-usability and portability. The accuracy of this new gate impedance model is demonstrated in various applications: to validate the model extraction techniques for different device configurations, to assess the input data run-length variations on CML buffer performance and to estimate the jitter in ring oscillators

    Compact modelling in RF CMOS technology

    Get PDF
    With the continuous downscaling of complementary metal-oxide-semiconductor (CMOS) technology, the RF performance of metal-oxide-semiconductor field transistors (MOSFETs) has considerably improved over the past years. Today, the standard CMOS technology has become a popular choice for realizing radio frequency (RF) applications. The focus of the thesis is on device compact modelling methodologies in RF CMOS. Compact models oriented to integrated circuit (ICs) computer automatic design (CAD) are the key component of a process design kit (PDK) and the bridge between design houses and foundries. In this work, a novel substrate model is proposed for accurately characterizing the behaviour of RF-MOSFETs with deep n-wells (DNW). A simple test structure is presented to directly access the substrate parasitics from two-port measurements in DNWs. The most important passive device in RFIC design in CMOS is the spiral inductor. A 1-pi model with a novel substrate network is proposed to characterize the broadband loss mechanisms of spiral inductors. Based on the proposed 1-pi model, a physics-originated fully-scalable 2-pi model and model parameter extraction methodology are also presented for spiral inductors in this work. To test and verify the developed active and passive device models and model parameter extraction methods, a series of RF-MOSFETs and planar on-chip spiral inductors with different geometries manufactured by employing standard RF CMOS processes were considered. Excellent agreement between the measured and the simulated results validate the compact models and modelling technologies developed in this work
    corecore