mm-Wave Silicon ICs: Challenges and Opportunities

Millimeter-waves offer promising opportunities and interesting challenges to silicon integrated circuit and system designers. These challenges go beyond standard circuit design questions and span a broader range of topics including wave propagation, antenna design, and communication channel capacity limits. It is only meaningful to evaluate the benefits and shortcoming of silicon-based mm-wave integrated circuits in this broader context. This paper reviews some of these issues and presents several solutions to them

Integrated Silicon Photonics for High-Speed Quantum Key Distribution

Integrated photonics offers great potential for quantum communication devices in terms of complexity, robustness and scalability. Silicon photonics in particular is a leading platform for quantum photonic technologies, with further benefits of miniaturisation, cost-effective device manufacture and compatibility with CMOS microelectronics. However, effective techniques for high-speed modulation of quantum states in standard silicon photonic platforms have been limited. Here we overcome this limitation and demonstrate high-speed low-error quantum key distribution modulation with silicon photonic devices combining slow thermo-optic DC biases and fast (10~GHz bandwidth) carrier-depletion modulation. The ability to scale up these integrated circuits and incorporate microelectronics opens the way to new and advanced integrated quantum communication technologies and larger adoption of quantum-secured communications

Integrated phased array systems in silicon

Silicon offers a new set of possibilities and challenges for RF, microwave, and millimeter-wave applications. While the high cutoff frequencies of the SiGe heterojunction bipolar transistors and the ever-shrinking feature sizes of MOSFETs hold a lot of promise, new design techniques need to be devised to deal with the realities of these technologies, such as low breakdown voltages, lossy substrates, low-Q passives, long interconnect parasitics, and high-frequency coupling issues. As an example of complete system integration in silicon, this paper presents the first fully integrated 24-GHz eight-element phased array receiver in 0.18-μm silicon-germanium and the first fully integrated 24-GHz four-element phased array transmitter with integrated power amplifiers in 0.18-μm CMOS. The transmitter and receiver are capable of beam forming and can be used for communication, ranging, positioning, and sensing applications

A fully integrated 24-GHz phased-array transmitter in CMOS

This paper presents the first fully integrated 24-GHz phased-array transmitter designed using 0.18-/spl mu/m CMOS transistors. The four-element array includes four on-chip CMOS power amplifiers, with outputs matched to 50 /spl Omega/, that are each capable of generating up to 14.5 dBm of output power at 24 GHz. The heterodyne transmitter has a two-step quadrature up-conversion architecture with local oscillator (LO) frequencies of 4.8 and 19.2 GHz, which are generated by an on-chip frequency synthesizer. Four-bit LO path phase shifting is implemented in each element at 19.2 GHz, and the transmitter achieves a peak-to-null ratio of 23 dB with raw beam-steering resolution of 7/spl deg/ for radiation normal to the array. The transmitter can support data rates of 500 Mb/s on each channel (with BPSK modulation) and occupies 6.8 mm /spl times/ 2.1 mm of die area

An Opportunistic Error Correction Layer for OFDM Systems

In this paper, we propose a novel cross layer scheme to lower power\ud consumption of ADCs in OFDM systems, which is based on resolution\ud adaptive ADCs and Fountain codes. The key part in the new proposed\ud system is that the dynamic range of ADCs can be reduced by\ud discarding the packets which are transmitted over 'bad' sub\ud carriers. Correspondingly, the power consumption in ADCs can be\ud reduced. Also, the new system does not process all the packets but\ud only processes surviving packets. This new error correction layer\ud does not require perfect channel knowledge, so it can be used in a\ud realistic system where the channel is estimated. With this new\ud approach, more than 70% of the energy consumption in the ADC can be\ud saved compared with the conventional IEEE 802.11a WLAN system under\ud the same channel conditions and throughput. The ADC in a receiver\ud can consume up to 50% of the total baseband energy. Moreover, to\ud reduce the overhead of Fountain codes, we apply message passing and\ud Gaussian elimination in the decoder. In this way, the overhead is\ud 3% for a small block size (i.e. 500 packets). Using both methods\ud results in an efficient system with low delay

The Future of High Frequency Circuit Design

The cut-off wavelengths of integrated silicon transistors have exceeded the die sizes of the chips being fabricated with them. Combined with the ability to integrate billions of transistors on the same die, this size-wavelength cross-over has produced a unique opportunity for a completely new class of holistic circuit design combining electromagnetics, device physics, circuits, and communication system theory in one place. In this paper, we discuss some of these opportunities and their associated challenges in greater detail and provide a few of examples of how they can be used in practice

Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio

A discrete-time (DT) mixing architecture for RF-sampling receivers is presented. This architecture makes RF sampling more suitable for software-defined radio (SDR) as it achieves wideband quadrature demodulation and wideband harmonic rejection. The paper consists of two parts. In the first part, different downconversion techniques are classified and compared, leading to the definition of a DT mixing concept. The suitability of CT-mixing and RF-sampling receivers to SDR is also discussed. In the second part, we elaborate the DT-mixing architecture, which can be realized by de-multiplexing. Simulation shows a wideband 90° phase shift between I and Q outputs without systematic channel bandwidth limitation. Oversampling and harmonic rejection relaxes RF pre-filtering and reduces noise and interference folding. A proof-of-concept DT-mixing downconverter has been built in 65 nm CMOS, for 0.2 to 0.9 GHz RF band employing 8-times oversampling. It can reject 2nd to 6th harmonics by 40 dB typically and without systematic channel bandwidth limitation. Without an LNA, it achieves a gain of -0.5 to 2.5 dB, a DSB noise figure of 18 to 20 dB, an IIP3 = +10 dBm, and an IIP2 = +53 dBm, while consuming less than 19 mW including multiphase clock generation